CS 370 - Autumn 2002
Introduction to Digital Design
Instructor: Carl Ebeling

Homework Set 7
DUE: Friday, Nov. 15 , 2002, Start of class

Collaboration Policy:

Unless otherwise noted, you may collaborate with other CSE370 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.

Late Homework Policy:

The weekly assignments are due at the beginning of class. Assignments handed in during or immediately after class will incur a 10% penalty. Your assignment will be penalized 10% per day for each additional day late.  Assignments due Friday will be charged 20% if turned in over the weekend, 30% if turned in on Monday, etc.

Please show all of your work.Your solutions must be legible…we will not spend time trying to decipher poorly written assignments.

Changes appear in RED.

1. (25 points)  The circuit in the hw7 folder called "reg1" implements a register using a circuit called an Earle latch ("latch1") that is based on a multiplexor.  (This latch was used in the Cray 1S supercomputer.)  When you simulate this register, you'll find that it doesn't work.  Figure out what the problem is and fix it.  Hand in the schematic of your fixed circuit.  (Hint:  You've seen this before!)

2. (25 points)  The circuit called DFF is yet another edge-triggered D register made from gates.  Using simulation (and stimulators), determine the following timing parameters for this register.  Measure in units of 1ns.
   tsetup - setup time.  Data must be valid at least this much time before the clock edge.
   thold - hold time.  Data must remain stable this long after the clock edge.
   tpd - propagation delay.  The delay from the clock edge to valid outputs.
   tcp - clock pulse time.  The clock must be high for at least this much time for the register to work.
Make sure you test both when the output is changing low-to-high and high-to-low and take the worst case.  Hint:  If you make two copies of the DFF and make the input to one the complement of the input to the other, you don't have to do two different simulations.  There are even cleverer ways to set up the simulation.
[Extra credit: Perform the same measurements for the register (fixed) in problem 1.  Which better?]

3. (100 points)  You have already designed the most complex component of your processor, the ALU.  When the ALU performs an operation, it needs two values for input and a place to store the output.  These values will be saved in the registers in what is called a register file.   Our register file contains four 16-bit registers numbered 0 to 3.  The ALU reads the values in two of these registers and the result is written back to a third.  This register file is shown in the figure below labeled regfile4x16.  The two addresses AddrA and AddrB indicate which register values are read to the A and B outputs, and AddrW indicates which register is to be written from the D input.  This register is written only if the Write input signal is asserted.  The reset signal is used to clear the registers in the register file.
    Design and test this register file using Active-HDL.  The test fixture tests your register file and ALU working together as shown below. On each clock cycle, it specifies an op-code for the ALU and three register addresses for the register file and makes sure that the result is correct.  You should change the clock period of the ClockGen to 20ns.  To do this, right-click on ClockGen, choose the Properties option and set the actual value of the parameter called "period" to 20.  (You have to recompile of course.)


To implement this register file, you will need to make 16 copies of things like registers.  You can do this either by actually making 16 copies. (Make the lower bit first with all the signals connected, then copy the whole thing.  You'll find that signals indices get automatically incremented.)  Or you can use the ARRAY feature.  Right click on the component you want to stack, and enter the number of copies you need.  Turn on the ARRAY text parameter so you know you've made an array of 16 copies.
WARNING:  Don't use ARRAYs inside of ARRAYs - there's a bug in the simulator that causes errors sometimes if you do this.