Introduction to Digital Design

Instructor: Carl Ebeling

Homework Set 5

**DUE: Friday, Nov. 8****
, 2002, Start of class**

**Collaboration Policy:**

Unless otherwise noted, you may collaborate with other CSE370 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.

**Late Homework Policy:**

The weekly assignments are due at the beginning of class. Assignments handed in during or immediately after class will incur a 10% penalty. We will penalize your assignment 10% per day for each additional day late.

Please show *all* of your work.Your solutions must be legible…we
will not spend time trying to decipher poorly written assignments.

1. (25 points) Implement the function f(A,B,C,D,E) = AB + C'D +BD' + B'D +B'CE using the following methods. Note that the quality of your solution will depend on how you factor the function, i.e. which variables you use for the selects of the multiplexor.

a) One 16-1 multiplexor plus inverters as necessary.

b) One 8-1 multiplexor plus AND, OR, and inverter gates
as necessary.

2. (25 points) Recall the problem from lecture where we designed a MaxMin
component which compared two input numbers and output the larger number on
one output and the smaller number on the other. Part of this design
was a comparator that compared the two input numbers and generated a control
which was used by the multiplexors on each output to select the appropriate
input. (We will assume that the numbers are unsigned.)

In this problem, you are design this comparator for
the case where the inputs are 3-bit numbers. The goal is to design
an efficient circuit. We will use the following cost model:

Logic gates: $1 per input

Multiplexors: $1 per input (data only, not select)

Decoders: $1 per output

(Hint: If the two input numbers are equal, do we care which output is selected
as the Max or Min?)

3. (50 points) In this assignment, you will implement and test a complete 16-bit carry-lookahead adder using Active-HDL. You will find test fixtures for each of the components and the final circuit in the HW5 folder. Make sure you use only components from the lib370 folder.

a) Design and test a 1-bit adder which has three inputs, A, B, Cin, and three outputs, Sum, P, and G, where P and G are the propagate and generate functions.

b) Using your 1-bit adder, design and test a 4-bit adder component which has three input busses, A[3:0], B[3:0], Cin[3:0] and three output busses, Sum[3:0], P[3:0] and G[3:0]. (This 4-bit adder is just four independent copies of the 1-bit adder.)

c) Design and test a 4-bit carry-lookahead component that has three inputs, P[3:0], G[3:0], Cin, and three outputs, Cout[3:0], BlockP, and BlockG. BlockP and BlockG are the block propagate and block generate functions.

d) Using your 4-bit adder component and 4-bit carry-lookahead component, design and test a 16-bit carry-lookahead adder.

e) What is the size (# of gates) and delay of your 16-bit carry-lookahead adder?

f) If you continued and made a 64-bit carry-lookahead adder using these components, what would be the size and delay of that circuit?