Reading Guide for the CSE 370 Textbook

Randy H. Katz, "Contemporary Logic Design" Benjamin-Cummings/Addison-Wesley, new edition (unpublished)

The text covers more material that we will cover in class, as is usual when a text is meant to be used for a semester.  The text also covers some material in a different order than we do in lectures.  For example, we will delay discussing Verilog until pretty late in the quarter - we don't need it until then.
The topics that we have already covered are colored in RED. Optional or omitted topics are in GREEN.

Text

Comments
Chapter 1
 Optional
 This is an overview of the area of digital design.  It will make more sense after you finish the class.
Appendix A +
Number Systems (from old text Ch. 5)
 Required
 Covers binary numbers, 1's and 2's complement representation, arithmetic on binary numbers,
conversions between bases
Chapter 2: p.31-47, 55-75
 Required
 Boolean Algebra, canonical forms, cubes, K-maps
                 p.47-54
 Required
 Circuit delays, hierarchy in circuits, case study
                 p.75-82
 Omit
 Multi-level logic (covered in CSE467)
Chapter 3: p.93-103, 108-110
 Required
 2-level logic minimization, K-maps, ESPRESSO algorithm
                 p.104-108
 Omit
 Quine-McCluskey method
                 p.111-114
 Required
 DeMorgan's law and logic gate equivalents
                 p.114-128
 Omit
 Multi-level logic minimization (covered in CSE467)
                 p.128-137
 Required
 Circuit timing and Hazards/Glitches (dynamic hazards optional)
                 p.138-145
Verilog intro (covered 2nd half of class)
Chapter 4: p.153-166
 Optional
 History of circuit technologies
                 p.166-182, 184-205
 Required
 ROMs, PLAs, PALs, decoders , multiplexers.  We are covering this in a different order, but all at the
same time as in the book.  Discussion of lookup-table based FPGAs (p. 195,202) is optional.
                 p.205-207
 Required
 Tri-state logic
                 p.208-212
 Optional
 Case-study, Wired-OR logic
Chapter 5: p.219-228
 Optional
 Case-studies
                 p.229-235
 Required
 		Case-studies
                 p.235-241,244-245
 Required
 		Ripple-carry adder, carry-lookahead adder, BCD adder
                 p.242-252
 Optional
 Carry-select adder, ALU, multiplier (covered in CSE467)
Chapter 6: p.257-270
 Optional**
 Details of latches and flip-flops - optional except for RS and master-slave RS flip-flops
                 p.270-282
 Required
 		Clocking, edge-triggered registers, latches, timing constraints, asynchronous inputs (simplified)
                 p.282-285
 Omit
 Self-timed circuits (covered in CSE467)
                 p.285-290
 Required
 		Registers, shift registers
                 p.290-295
Verilog for sequential circuits
Chapter 7: p.329-337
 Optional
 		TTL parts for registers, shift registers, counters.  Largely obsolete.
                 p.338-345
 Supplementary
 Counter design - supplement to class notes.  T and JK flip-flops optional.
                 p.345-351
 Supplementary
 Implementation with different flip-flops.  Focus on D flip-flops.
                 p.352-356
 Supplementary
 Using counters - supplement to class notes.
                 p.356-372 Omit
 Memory systems are covered in 467
Chapter 8: p.383-388
 Required
 State machine introduction
                 p.388-395
 Required
 State machine implementation (ignore JK registers)
                 p.395-398
 Required
 ASM representation of state machines
                 p.398-402
 Omit
 VHDL/ABEL descriptions of state machines
                 p.402-412
 Required
 Mealy/Moore machine design procedures
                 p.412-432
 Required
 State machine design case studies (ignore ABEL)  Supplements class material




Comments to: cse370-webmaster@cs.washington.edu (Last Update: 09/27/02 )