CSE 370

This is the schedule of lectures, related readings, and homework and exam dates.
You can expect a homework assignment every week. Assignments will typically be handed out on Wednesday in class, and due the following Friday at the beginning of class. We may ask you to submit assignments done using the CAD Tools (ActiveHDL) electronically. We will give you instructions on how to do this.
The last column indicates the pages of the textbook that are relevant to the lecture material. It is an excellent idea to read over this before it is covered in class. The textbook is also a good source of additional explanations and examples.
Week  Day  Date  Topic  Textbook reading 
#1  M  9/30 
Introduction and Course Overview  
W  10/2 
Binary numbers, Boolean
algebra Assignment #1 distributed 
Appendix A pp. 3139 

F  10/4 
Boolean algebra and theorems, gates  pp. 4049  
#2  M  10/7 
2level logic, canonical forms  pp. 5061 
W  10/9  Graphical representations of Boolean
functions Assignment #2 distributed 
pp. 6270 

F  10/11 
Karnaugh Maps/Logic minimization Assignment #1 due; Quiz 1 
pp. 7175  
#3 
M 
10/14 
2level logic simplification  pp. 93103 
W 
10/16 
2level logic simplification 
no QuineMcCluskey Assignment #3 distributed 
pp. 111114 

F 
10/18 
Combinational logic delay and glitches Assignment #2 due 
pp. 128135 

#4 
M 
10/21 
Structured logic implementation; decoders  pp. 153170 
W 
10/23 
PLAs, PALs: Espresso algorithm Assignment #4 distributed 
pp. 108110, 171182 

F 
10/25 
ROMs,
multiplexers Assignment #3 due; Quiz 2 
pp. 184195 

#5 
M 
10/28 
Nongate logic: Tristate and opencollector
drivers 
pp. 205212 
W 
10/30 
Adders; carry lookahead Assignment #5 distributed 
pp. 235239 

F 
11/1 
ALU, multiplier design Assignment #4 due 
pp. 240251 

#6 
M 
11/4 
Sequential logic: registers and clocks  pp. 267278 
W 
11/6 
Enabled registers, shift registers Assignment #6 distributed 
pp. 286290 

F 
11/8 
Counters,
register files Assignment #5 due; Quiz 3 
Class notes 

#7 
M 
11/11 
Holiday  Veteran's Day 

W 
11/13 
Datapath/Control Assignment #7 distributed 
Class notes 

F 
11/15 
State machines, state diagrams Assignment #6 due 
pp. 383395, class notes 

#8 
M 
11/18 
Mealy vs. Moore FSMs Implementing FSMs 
pp. 403417, class notes 
W 
11/20 
Implementing FSMs Assignment #8 distributed 
pp. 418431 

F 
11/22 
Simple
processor design Assignment #7 due; Quiz 4 
Class notes 

#9 
M 
11/25 
Simple processor design  Class notes 
W 
11/27 
Verilog HDL: combinational logic Assignment #9 distributed 
Class notes 

F 
11/29 
Holiday  Thanksgiving 

#10 
M 
12/2 
Verilog HDL: sequential logic 
Class notes 
W 
12/4 
More Verilog: examples Assignment #8 due 
Class notes 

F 
12/6 
Clock
skew; asynchronous inputs Quiz 5 
pp. 275285 

#11 
M 
12/9 
Review; catchup 

W 
12/11 
Review; catchup Assignment #9 due 

T12:30 
12/17 
Final Exam, Sieg 134 
Other UW Time Schedules
Autumn 2002 final exam schedule (CSE370 final exam may differ in time)