CSE370 Assignment 3

Distributed: 24 January 2001
Due: 2 February 2001

Reading:

1. Katz, Chapter 2 (pages 40-85).
2. Katz, Chapter 3 (pages 112-115).

Exercises:

1. Consider the following three-input logic function f(X,Y,Z) = (X+Y)(X'+Y'+Z)(X+Y'+Z')(Y+Z'). 
   a) Convert the function into a S-O-P form using DML.
   b) Find both the minimal S-O-P and P-O-S form of this function.
   c) Using DesignWorks implement the above function in the form you obtained in (a) and in the minimal P-O-S form. Generate two timing diagrams, one for each form, for all input (X,Y,Z) transitions when exactly two inputs are changed quazi-simultaneously. Assume that all gates have zero delay.
   Submit printouts of: your circuit, test vector file and timing diagram.
2. Consider the problem 2.18 (a-f) from Katz (page 106). 
   a) Find the minimal S-O-P form for the inverted version of each function f().
   b) Implement all resulting minimal forms using NAND gates with invertible inputs.
3. Create a four-input function that has at least three different minimal P-O-S forms.
4. Consider a 4-input 4-output function that outputs the succeeding number of a 4-bit Gray code. 
   a) Find a minimal S-O-P form of each of the outputs using Karnaugh-maps.
   b) Can you reduce the number of gates on any of the four functions if XOR gates are allowed in the implementation.
   c) For each function (output) replace at most one TRUE output with a FALSE output to achieve maximal reduction of the number of used gates (AND,OR,NOT) in the minimal S-O-P form.
5. Consider the four output functions from the previous problem. Assume that the output for inputs (3,7,9,12) is "don't care".
   a) Find the minimal P-O-S form of each output using Karnaugh maps.
   b) Implement each output using NOR gates with invertible inputs.
   c) Denote the prime implicants of each function.

Rationale:

• To practice and gain facility with two-level canonical forms.
• To practice basic combinational logic design.