# Solutions for Homework #7

1. Block Diagram: Code:

module Adder_4bit(A0, A1, A2, A3, B0, B1, B2, B3, Cin, S0, S1, S2, S3, Cout);

input              A0;

input              A1;

input              A2;

input              A3;

input              B0;

input              B1;

input              B2;

input              B3;

input              Cin;

output      S0;

output      S1;

output      S2;

output      S3;

output      Cout;

reg[4:0] A;

reg[4:0] B;

reg[4:0] Sum;

assign A = {A3, A2, A1, A0};

assign B = {B3, B2, B1, B0};

assign Sum = A + B + Cin;

assign Cout = Sum;

assign S3 = Sum;

assign S2 = Sum;

assign S1 = Sum;

assign S0 = Sum;

endmodule

2. 3.

 S2 S1 S0 S1 S0 LSI RSI 0 0 0 0 0 X X 0 0 1 0 1 X D 0 1 0 1 0 A X 0 1 1 0 1 X 0 1 0 0 1 0 0 X 1 0 1 0 1 X A 1 1 0 1 0 0 X 1 1 1 1 1 X X I began solving this problem by constructing a truth table of the inputs S2, S1, and S0 with the outputs being S1, S0, SRSER, and SLSER of the 74194 general shifter part.  (Truth table reproduced above).  I used standard K-Map methods to simplify the control signals, resulting in the logic above for S1 and S0.  Next, I looked at when we need to care about the Left shift input, resulting in the 3 gates below (Note that this effectively just implements a 2:1 MUX).  As the right shift input was a function of 2 control signals, I used a 4:1 MUX to select the correct signal.

4. This is my (slightly improved) version of a flow-through FIFO queue.  Note that some of these features were unnecessary for the homework turn in.  First, our state (whether we are expecting pushes or pops) is stored in the R-S Latch up above.  If it holds a 1, we are expecting a push command.  The 2 AND gates (labled Allow_Push and Allow_Pop) pass through a valid command if we are in that state.  For example, if we are expecting a pop (state = 0), then Allow_Push will be 0, and Allow_Pop will be whatever Pop’s value is.  Next, we and these with the clock input.  This functions to select only clock edges where a command is given.  This is my clock signal for the shift registers.  Since the registers shift each time a positive edge of the clock is seen, we must protect it from edges where push and pop are both zero (i.e. do no operation).  The addition of an OR after the clock signal generation serves to create an asynchronous reset pulse, given by the input RST (note that this is inverted – 0 resets).

As a last piece of set up, I use 4 2:1 MUXes (the large block on the bottom – standard Designworks part).  If we are poping, we actually must push something into the holes left behind by the values moving forward.  This mux chooses between the input pins in Push mode, and zero’s in Pop mode.  This gives the nice characteristic that when the queue is emptied, it looks identical to reset.

The actual shifting is done with 5 general shift registers, found in the Primlog library of Designworks.  Words are constructed horizontally through the first 4, with the queue “index” moving vertically.  The fifth register serves as a “valid” bit, noting which elements were Pushed in, and which are filler from Pops.

Lastly, as suggested in class, I added a Valid output, which indicates when the output value was one pushed in, or whether it is a just a “filler” output.