# Sequential logic implementation

#### 5/17/00

Sequential logic implementation

Abstraction of state elements

Forms of sequential logic

Finite state machine representations

Example finite state machine diagram

Can any sequential system be represented with a state diagram?

Counters are simple finite state machines

How do we turn a state diagram into logic?

FSM design procedure

FSM design procedure: state diagram to encoded state transition table

Implementation

Implementation (cont'd)

Another example

More complex counter example

More complex counter example (contĺd)

Self-starting counters (contĺd)

Self-starting counters

State machine model

State machine model (contĺd)

Example: ant brain (Ward, MIT)

Ant behavior

Designing an ant brain

Synthesizing the ant brain circuit

Transition truth table

Synthesis

Synthesis of next state and output functions

Circuit implementation

Donĺt cares in FSM synthesis

State minimization

Ant brain revisited

New improved brain

New brain implementation

Mealy vs. Moore machines

Specifying outputs for a Moore machine

Specifying outputs for a Mealy machine

Comparison of Mealy and Moore machines

Mealy and Moore examples

Mealy and Moore examples (contĺd)

Registered Mealy machine (really Moore)

Example: vending machine

Example: vending machine (contĺd)

Example: vending machine (contĺd)

Example: vending machine (contĺd)

Example: vending machine (contĺd)

Example: vending machine (contĺd)

Equivalent Mealy and Moore state diagrams

Example: traffic light controller

Example: traffic light controller (contĺ)

Example: traffic light controller (contĺ)

Example: traffic light controller (contĺ)

Example: traffic light controller (contĺ)

Logic for different state assignments

Vending machine example (PLD mapping)

Vending machine (contĺd)

Vending machine (retimed PLD mapping)

Finite state machine optimization

Algorithmic approach to state minimization

State minimization example

Method of successive partitions

Minimized FSM

More complex state minimization

Minimized FSM

Minimizing incompletely specified FSMs

Minimizing states may not yield best circuit

Another implementation of edge detector

State assignment

State assignment strategies

One-hot state assignment

Heuristics for state assignment

General approach to heuristic state assignment

Output-based encoding

Current state assignment approaches

Sequential logic implementation summary

Author: Gaetano Borriello