Table of ContentsSequential logic Sequential circuits Circuits with feedback Simplest circuits with feedback Memory with cross-coupled gates Timing behavior State behavior or R-S latch Theoretical R-S latch behavior Observed R-S latch behavior R-S latch analysis Gated R-S latch Clocks Clocks (cont’d) Cascading latches Master-slave structure The 1s catching problem D flip-flop Edge-triggered flip-flops Edge-triggered flip-flops (cont’d) Edge-triggered flip-flops (cont’d) Timing methodologies Timing methodologies (cont’d) Comparison of latches and flip-flops Comparison of latches and flip-flops (cont’d) Typical timing specifications Cascading edge-triggered flip-flops Cascading edge-triggered flip-flops (cont’d) Clock skew Summary of latches and flip-flops Metastability and asynchronous inputs Synchronization failure Dealing with synchronization failure Handling asynchronous inputs Handling asynchronous inputs (cont’d) Flip-flop features Registers Shift register Universal shift register Design of universal shift register Shift register application Pattern recognizer Counters Binary counter Four-bit binary synchronous up-counter Offset counters Sequential logic summary |
Author: Gaetano Borriello |