Table of ContentsCombinational logic implementation Implementations of two-level logic Two-level logic using NAND gates Two-level logic using NAND gates (cont’d) Two-level logic using NOR gates Two-level logic using NOR gates (cont’d) Two-level logic using NAND and NOR gates Conversion between forms Conversion between forms (cont’d) Conversion between forms (cont’d) Conversion between forms (cont’d) Multi-level logic Conversion of multi-level logic to NAND gates Conversion of multi-level logic to NORs Conversion between forms AND-OR-invert gates Conversion to AOI forms Examples of using AOI gates Examples of using AOI gates (cont’d) Summary for multi-level logic Time behavior of combinational networks Momentary changes in outputs Oscillatory behavior Hazards/glitches Types of hazards Static hazards Dynamic hazards Making connections Mux and demux Mux and demux (cont'd) Multiplexers/selectors Multiplexers/selectors (cont'd) Gate level implementation of muxes Cascading multiplexers Multiplexers as general-purpose logic Multiplexers as general-purpose logic (cont’d) Multiplexers as general-purpose logic (cont’d) Demultiplexers/decoders Gate level implementation of demultiplexers Demultiplexers as general-purpose logic Demultiplexers as general-purpose logic (cont’d) Cascading decoders Programmable logic arrays Enabling concept Before programming After programming Alternate representation for high fan-in structures Programmable logic array example PALs and PLAs PALs and PLAs: design example PALs and PLAs: design example (cont’d) PALs and PLAs: design example (cont’d) PALs and PLAs: design example (cont’d) PALs and PLAs: another design example Read-only memories ROMs and combinational logic ROM structure ROM vs. PLA Regular logic structures for two-level logic Regular logic structures for multi-level logic Combinational logic implementation summary |
Author: Gaetano Borriello |