CSE 370 Spring 2000
Solutions for Homework 7
05/22//2000
Problem 1
Verilog Code
module ShiftReg(D0, D1, D2, D3, D, S0, S1, Clk, Q0, Q1, Q2, Q3);
input D0;
input D1;
input D2;
input D3;
input D;
input S0;
input S1;
input Clk;
output Q0;
output Q1;
output Q2;
output Q3;
reg QO, Ql, Q2, Q3;
reg[3:0] indata;
reg[3:0] out;
reg[3:0] nextout;
reg[2:0] sel;
assign indata = {D3,D2,D1,D0};
assign sel = {S1,S0, D};
// State Definitions
`define Load1
3'b000
`define Load2
3'b001
`define CircularShiftLeft
3'b010
`define CircularShiftRight 3'b011
`define LogicalShiftLeft
3'b100
`define LogicalShiftRight
3'b101
`define ArightmeticShiftLeft 3'b110
`define ArightmeticShiftRight 3'b111
/* clock driven "state" transitions */
always @(posedge Clk) begin
out = nextout;
$display("Input is %b, Sel is %d, Output is
%b", indata, sel, out);
end
/* combinational logic to determine next output */
always @(out or sel or indata) begin
case(sel)
`Load1: nextout = indata;
`Load2: nextout = indata;
`CircularShiftLeft: nextout = {out[2:0],
out[3]};
`CircularShiftRight: nextout =
{out[0], out[3:1]};
`LogicalShiftLeft: nextout = {out[2:0],
1'b0};
`LogicalShiftRight: nextout = {1'b0,
out[3:1]};
`ArightmeticShiftLeft: nextout = {out[2:0],
1'b0};
`ArightmeticShiftRight: nextout = {out[3],
out[3:1]};
endcase
end
assign Q3 = out[3];
assign Q2 = out[2];
assign Q1 = out[1];
assign Q0 = out[0];
endmodule
Testing Setup
Timing Waverform
Problem 2
Register circuit
Testing Setup
Problem 3
Verilog Code
module GrayCounter(En, Reset, Clk, Q0, Q1, Q2);
input En;
input Reset;
input Clk;
output Q0;
output Q1;
output Q2;
reg QO, Ql, Q2;
reg[2:0] out;
reg[2:0] nextout;
/* clock driven "state" transitions */
always @(posedge Clk) begin
out = nextout;
end
/* combinational logic to determine next output */
always @(out or Reset or En) begin
if (Reset)
nextout = 3'b110;
else
if (!En)
nextout = out;
else
case(out)
3'b000: nextout = 3'b001;
3'b001: nextout = 3'b011;
3'b010: nextout = 3'b110;
3'b011: nextout = 3'b010;
3'b100: nextout = 3'b000;
3'b101: nextout = 3'b100;
3'b110: nextout = 3'b111;
3'b111: nextout = 3'b101;
endcase
end
assign Q2 = out[2];
assign Q1 = out[1];
assign Q0 = out[0];
endmodule
Testing Setup
Timing Waveform
