## CSE370 Assignment 7

### Distributed: 5 May 1999 Due: 12 May 1999

1. Katz, Chapter 4 (pp. 194-202).
2. Katz, Chapter 7 (pp. 337-345, 352-356).
3. Katz, Chapter 8 (pp. 383-395).

#### Exercises:

1. In Verilog, design the shifter described in Katz's Problem 7.2. Do not use the 74194 TTL part, instead, design your own shifter starting with 4 D-flip-flops (in Verilog, this is simply a variable declared as reg[3:0]). You will have 3 control signals. The first two (S1 and SO) will control the type of shift: 00 meaning load a new value; 01 for circular; 10 for logical; and 11 for arithmetic. The third control input (D) will set the direction of the shift: 0 for left; 1 for right. Turn in a simulation waveform that shows the shifter being loaded with "1001" then circular shift right, arithmetic shift right, and logic shift right. Follow this with an arithmetic shift left, circular left, and logic left. Make sure your simulation waveform clearly shows the control inputs changing as well as the outputs. You can use switches to set the control inputs and set the simulator speed to something slower than RUN. This will let you change the inputs at reasonably close intervals from one another without the waveform "running away" on you because of a fast moving clock. If you prefer, (and actually don't mind writing more Verilog) you can also set up a stimulus module to drive your simulation that includes an `always` block with the clock in its sensitivity list. This will execute once per clock cycle so that you can advance the control signals through the sequence above.
2. Using just the basic D flip-flop and combinational logic, design a 4-bit register with a load input (load) and an input select (sel) to choose which of two possible 4-bit inputs (A or B) to load.  Do this with a DesignWorks schematic. Come up with your own test cases to verify it works correctly.
3. Create a counter that counts in Gray code (000, 001, 011, 010, 110, 111, 101, 100, 000, ... ). It should have a reset signal that sets it to 110 and an enable input that stops the counter (holds the current value) when low. Do this in Verilog using a "case" statement. (Hint: Follow good design practices and layout a transition table and/or state diagram before doing the Verilog implementation.) For your simulation, start with it disabled. Reset it (leaving it disabled; it should reset even while disabled) for two cycles, then lower reset but leave it disabled for two cycles. Enable it and let it run for ten (10) cycles. Reset it (but leave it enabled) for two cycles, then lower reset for two more cycles.

#### Notes:

Learn to use `\$display` statements to show what's going on inside a Verilog module. Display statements are documented in the LVM (Verilog) manual on page 56. You have to put them inside an `always` block. In a Verilog module, you can display individual bits, using the `%b` specifier, or vectors using the `%h` specifier. Put this `\$display` statement at the bottom of your `always` block.

You can use screen shots to show that your simulation is working including showing us the contents of LVM windows. Use Alt-PrintScreen to take a snapshot of the current window, or Ctl-PrintScreen to grab the entire screen. Now your image is on the clipboard and you can import into your favorite editor. Make sure to always clearly label everything with which submodule and which test case it represents.

Of course, you should turn in printouts of all of your circuits, subcircuits, and verilog models. Remember that printers can print duplex (2-sided) so save a tree if possible.

Finally, remember to create and save library parts for everything you build in this assignment. It is very likely that you will be asked to use these parts as part of another design in subsequent assignments.

#### Rationale:

• To develop an understanding of basic sequential logic elements.
• To be able to design simple sequential logic circuits such as registers and counters.
• To use a hardware description language for the specification of sequential logic.

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