module StuffFrame(E, A, U, S, V, Clk, Reset);    
input         E;
output        A;
input         U; 
output        S; 
output        V; 
input         Clk; 
input         Reset;
reg           V; 
reg           S; 
reg           A;

/* Internals */ 
reg [6:0]     state; 
reg [6:0]     next_state;

/* State encoding {V, S, A} + 4 extra bits                 */
`define START   7'b0000000 /* wait for enable              */ 
`define BEGIN1  7'b1100000 /* send 1st bit of begin marker */ 
`define BEGIN2  7'b1100001 /* send 2nd bit of begin marker */ 
`define BEGIN3  7'b1100010 /* send 3rd bit of begin marker */ 
`define BEGIN4  7'b1010011 /* send 4th bit of begin marker */
`define SEND0   7'b1011000 /* send a zero                  */
`define SEND1   7'b1111001 /* send a one                   */
`define STUFF   7'b1101010 /* send a one & hold next input */ 
`define END1    7'b1100100 /* send 1st bit of end marker   */  
`define END2    7'b1100101 /* send 2nd bit of end marker   */ 
`define END3    7'b1100110 /* send 3rd bit of end marker   */
`define END4    7'b1000111 /* send 4th bit of end marker   */ 

/* State flip-flops with reset */
always @(posedge Clk) begin 
if (Reset) begin state = `START; end 
else begin state = next_state; end
end                                                                                                                                                                                                       /* Next state logic */ 

always @(E or U or state) begin
case(state) 
 `START:  if (E) next_state = `BEGIN1;
 else next_state = `START; 
 `BEGIN1: next_state = `BEGIN2;
 `BEGIN2: next_state = `BEGIN3;
 `BEGIN3: next_state = `BEGIN4;
 `BEGIN4: if (U) next_state = `SEND1; 

else next_state = `SEND0; 
 `SEND0:  if (~E) next_state = `END1; 

else if (U) next_state = `SEND1; 

else next_state = `SEND0; 
`SEND1:  if (~E) next_state = `END1;
 else if (U) next_state = `STUFF;