Edge-triggered flip-flops

negative edge-triggered D flip-flop (D-FF)

4-5 gate delays

must respect setup and hold time constraints to successfullycapture input

characteristic equationQ(t+1) = D

holds D' when

clock goes low

holds D whenclock goes low

• More efficient solution: only 6 gates

  • sensitive to inputs only near edge of clock signal (not while high)

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