module vendingMachineFSM_tb ();
  logic clk, reset, n, d;
  logic open;
 
  vendingMachineFSM dut (.clk, .reset, .n, .d, .open);
  
  // Set up the clock.
  parameter CLOCK_PERIOD=100;
  
  initial begin
	  clk <= 0;
	  forever #(CLOCK_PERIOD/2) clk <= ~clk;
  end
  
  // Design inputs.  Each line is a clock cycle.
  initial begin
    reset <= 1; n <= 0; d <= 0; @(posedge clk);
                    reset <= 0; @(posedge clk);
                                @(posedge clk);
                                @(posedge clk);
                        d <= 1; @(posedge clk);
                        d <= 0; @(posedge clk);
                        n <= 1; @(posedge clk);
                        n <= 0; @(posedge clk);
                        n <= 1; @(posedge clk);
                                @(posedge clk);
                  n <= 0; d<=1; @(posedge clk);
                          d<=0; @(posedge clk);
    $stop;  // End the simulation
  end
  
endmodule  // vendingMachineFSM_tb