Lab 5: Sequential Logic

Task 1 – Mapping Sequential Logic to the FPGA

To understand the sequential logic design, simulation, and execution process we'll use a state machine that has one input w and one output out. The output is true whenever w has been true for the previous two clock cycles (i.e., it recognizes the input sequence 1,1). The SystemVerilog code for the machine is given in simpleFSM.sv (code).

Simulation

To simulate this logic, we not only have to provide the inputs, but must also specify the clock. For that, we can embed some extra logic in the test bench. The test bench for this FSM is found in simpleFSM.sv (code). Simulate the design with ModelSim, and make sure that it works as you expect.

ModelSim Tip for sequential logic waveform viewing:

Clocks are really important to FSMs, so it is useful to set ther grey gridlines in the Wave pane to line up with the positive edger of the clocks. Click on the "Edit Grid & Timeline Properties…" icon in the lower-left corner of the Wave pane:

Set the "Grid Period" to 100 ps, which is the simulation clock period (set by parameter CLK_PERIOD = 100;), and the grid lines will line up with the clock. Make sure to save the formatting to the simpleFSM_wave.do file!

Hardware Implementation

To set up the design to run on the FPGA, we need to connect a (real) clock to the circuit, but the clocks on the chip are very fast (50 MHz is a clock cycle every 20 ns). We'd like to use a slower clock, so we provide a clock divider – a circuit that generates slower clocks from a master clock. DE1_SoC.sv (code) is a top-level module that includes a clock divider defined in clock_divider.sv (code) and sets up simpleFSM to use the LEDs and push buttons.

Add the new DE1_SoC.sv and clock_divider.sv to your project, synthesize the design for the FPGA, and test it on the DE1. This design uses KEY0 for reset (i.e., press to reset the circuit) and KEY1 as the w input. LEDR5 shows the clock, LEDR3 shows the reset, and LEDR0 shows the output of the FSM.

You do not have to demonstrate this circuit working, but running this test will help a LOT in getting the design problem working.

Task 2 – Runway Landing Lights

The landing lights at the SeaTac airport are busted, so we have to come up with a new set. In order to show pilots the wind direction across the runways, we will build special wind indicators to put at the ends of all runways at SeaTac.

Your circuit will be given two inputs (SW[1] and SW[0]), which indicate wind direction, and three output LEDs (LEDR[2:0]) to display the corresponding sequence of lights:

SW[1]

SW[0]

Meaning

Repeating Pattern

Illustration

0

0

Calm

P0: 1 0 1
P1: 0 1 0

0

1

Right to Left

P0: 0 0 1
P1: 0 1 0
P2: 1 0 0

1

0

Left to Right

P0: 1 0 0
P1: 0 1 0
P2: 0 0 1

For each situation, the lights should cycle through the given pattern. In a "Calm" wind, the lights will cycle between the outside lights lit, and the center light lit (two patterns), over and over again. The "Right to Left" and "Left to Right" crosswind indicators repeatedly cycle through three patterns each, which makes the light "move" from right to left or left to right, respectively.

The switches should never both be True. The switches may be changed at any point during the current cycling of the lights, and the lights must switch over to the new pattern as soon as possible. However, it can enter into any point in the other situation's pattern.

1. Draw an FSM diagram that uses two input bits and three output bits to implement the runway landings lights described above. Make sure you include a "reset" transition. Include the diagram in your lab report.
   
   Think carefully about your FSM design! There are multiple ways to do this task, but it's possible to design an FSM that only needs 4 states
   
   
   Drawing FSM diagrams will generally be your first step when working on sequential circuits. We will expect to see these drawings for all FSMs in future labs.
2. Once you have your FSM drawn, implement runway_lightsFSM in SystemVerilog.
3. Create a test bench runway_lightsFSM_tb to test your FSM thoroughly. Include an annotated screenshot (or screenshots) of this simulation in your report with a description of how it proves your FSM functions as expected.
4. Add your FSM to the top-level module DE1_SoC , replacing the simpleFSM instance. Synthesize it and make sure it runs correctly on the DE1 board.

Task 3 – Resource Utilization

After you've synthesized your circuit in Quartus, take a look at the Compilation Report (see figure below). In the left-hand column, select "Analysis & Synthesis" → "Resource Utilization by Entity."

This report breaks down how the various modules in our project take up space on the FPGA. The "Combinational ALUTs" column lists the # of FPGA logic elements being used, and the "Dedicated Logic Registers" is the # of DFFs in use. Each row corresponds to a given module, with the number in parentheses representing the resources just from that module (and not any submodules inside of it), while the number outside of the parentheses is the total resource count (including submodules).

1. Include a screenshot of this utilization report in your lab report.
2. Calculate your "resource score" by adding the numbers outside the parentheses for the entire design under "Combinational ALUTs" and "Dedicated Logic Registers." and then subtracting the result from that the same numbers from the "clock_divider" line. Include this calculation in your report as wellFor example, the simpleFSM from the first part of this lab has a score of (28+28)-(26+26) = 4, though obviously it doesn't perform the right functions for the runway lights…
3. Locate the resource usage report file output_files/DE1_SoC.map.rpt in your project directory. Submit this file alongside your report PDF and your SystemVerilog code. Gradescope will report your resource utilization to a Leaderboard, where students can compare their Resource Utilization for fun. When you submit you can choose the name that appears to the rest of the class next to your resource score; feel free to pick an anonymous name if you like!
   Note: This is the first quarter we've used the leaderboard feature and we've only tested our autograder on report output from Quartus 17.0.0 (the version available on our course website). In theory it should work for other versions as well, but if it crashsed or doesn't seem to be getting your resource score properly, please let us know in an Ed thread!

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