Lab 4: High-Level Verilog

Task 1 – Seven-Segment Displays

In lecture, we presented a seven-segment display driver. RTL code for that seven-segment display is given above (code).

1. Create a new project in Quartus Prime and add the seg7 code to it.
2. Create a new module, double_seg7, that uses two instances of the seg7 code – one that uses SW3-SW0 as inputs and outputs to HEX0, and another that uses SW7-SW4 as inputs and outputs to HEX1.
3. Create a corresponding test bench double_seg7_tb that verifies the behavior of your top-level module.
4. Test your module out on hardware. Try entering numbers using the switches and confirming those numbers appear on the seven-segment displays.

Task 2 – UPC Code to Display

In Lab 3, we built a system that took in a UPC and output whether a returned Nordstrom item was on sale for a discount and whether it was stolen. A nearby store, McCluskey's Pawn Shop, buys used items from customers that were originally purchased from various stores that also use the UPC system. Old Mr. McCluskey wants a similar item-checking system, but has found that devious customers are changing the UPC stickers on the items they are selling to misrepresent the price. To combat that, Mr. McCluskey would like you to add a display on HEX5-HEX0 that describes the product corresponding to that UPC – if the description doesn't match the item, then someone is trying to cheat Mr. McCluskey!

1. Make a new Quartus project with a top-level module named pawn_shop. Copy your nordstrom module over to this project too, you're going to use it later.
2. Come up with exactly six new items to fill out the leftmost column of the table below – three expensive items and three inexpensive items. You are not allowed to use any of the items from Lab 3 or the example given below. You are also not allowed to change any of the values in the "expensive" or "discounted" columns. Just change the names.
   
   Since we only have six 7-segment displays, you should consider what items will lend themselves to "good" (easily-distinguishable) displays.
   
   
   Item Name

   UPC

   Discounted?

   Expensive?

   <New Item 1>

   0 0 0

   No

   Yes

   <New Item 2>

   0 0 1

   No

   No

   <New Item 3>

   0 1 1

   Yes

   No

   <New Item 4>

   1 0 0

   No

   Yes

   <New Item 5>

   1 0 1

   Yes

   Yes

   <New Item 6>

   1 1 0

   Yes

   No
3. Determine corresponding 7-segment encodings for your six items. The displays do not need to use the entire item name, but they need to be at least 3 letters each and easily-distinguishable from the other UPC descriptions. You may use upper- and lower-case letters or pictograms.
   
   Example: The item "Dress Shoe" could be displayed as
   
   
   There is no "correct" way to encode the entire alphabet on 7-segment displays. You may use online resources such as http://tinyurl.com/h99785g or https://www.youtube.com/watch?v=RTB5XhjbgZA for inspiration, but you should decide for yourself whether or not your display is easily read or more of a stretch to interpret correctly.
4. Draw a block diagram for a circuit that implements the above functionality. It should be called upc_display and have three inputs (U, P, and C), similar to the seg7 module, but will instead have six 7-bit outputs for the 7-seg displays. Each output should be driven by a 7-bit 6-to-1 multiplexor, illustrated with standard "trapezoid" notation. Be sure to label the select value for each mux inputs and indicate the bit width of every bus in your diagram. If you're unsure whether you're using correct notation, ask your course staff.
5. Translate your circuit diagram to RTL code in Verilog, using case statements to implement your diagram's multiplexors.
6. Create a test bench upc_display_tb. Simulate your module thoroughly in ModelSim to make sure it works.
7. Draw a block diagram for your lab's top level module pawn_shop that shows an instance of upc_display and an instance of nordstrom sitting next to eachother. The design should use them both so the system simultaneously computes the Discounted LED, Stolen LED, and HEX displays. Make sure the diagram shows what board peripherals each module is connected to.
8. Write the Verilog implementation of pawn_shop based on your block diagram. Create a corresponding test bench pawn_shop_tb that verifies the behavior of your top-level module. Test and debug with ModelSim, then load onto your board.

Task 3 – Don't Cares

Your design has outputs for only 6 of the 8 possible UPC codes. For the other two cases, a line such as "default: LEDs = 7'bX;" tells Quartus Prime that it can treat these cases as a Don't Care condition. If you didn't do this, go back and correct it to do so. Test your design on the circuit board, and record the pattern it shows for these Don't Care conditions (hand drawn or photo will work).

Rubric