The first lab will introduce you to the Altera’s Terasic DE1-SoC development board and our primary design tool this quarter, Intel's Quartus Prime. These components are very important for all future labs so please pay attention. This lab outlines our expectations for reports and demos.
The designs in this class will be done through the Intel Quartus Prime software. This is preloaded on machines in the lab (CSE 003), and you are free to do all the work on these PCs. However, you can install the software on your own computer, if desired, by following the page.
Open the and complete Sections 0 through 8. Please ignore references to the *_tb.sv files in sections 2.2, 7.1, and 7A.1. Be sure to do all of the steps and ask the course staff for help when you encounter issues.
Now let's draw some block diagrams. The following mux2_1 diagram shows its two data inputs, select input, and output. The 0 and 1 written inside the trapezoid show which input is chosen for each value of the select signal. Look at the mux2_1 module and compare it to its schematic symbol.
Read through the document. Make sure you know where the LEDs, switches, and push buttons are on the DE1 and then connect it to your computer and power on your board. Feel free to play around with preloaded program to get a feel for the board inputs and outputs.
Now finish the rest of the Quartus Tutorial to program your board with the provided top-level module lab1.sv (code). Refer to the code comments and play with the appropriate inputs to discern the logical behaviors of our input and output signals.
Answer:
Now modify lab1.sv to implement the following additional logic. You will only need to add one line of code beneath each TODO comment. Refer to Lecture 2 for the syntax for gate modules and logical operators.
Re-synthesize your modified project and load it onto your board to make sure that it behaves as you would expect. Don't forget to upload your modified lab1.sv alongside your lab report.
You can earn up to 48 points for correctness, style, and testing.
Submit a zip file containing your lab report and finished/modified source files on due on Wednesday, April 8 at 2:30 pm.
Your zip file should contain:
Your report should contain the following:
Demos are due during your assigned slot. Rescheduling is only permitted if you turned your lab report in later than your demo time or have extenuating circumstances and prior approval by course staff. In any case, it must be completed by end of day Friday of the week your lab report was submitted.
Preparing & Setting Up:
During Your Demo: