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Homework Overview

Homework will be available on this page. Each assignment will be out on Friday and due the next Friday. Solutions will be posted at least 72 hours after the deadline to accommodate anyone who has obtained an extension.

Homework will be posted in both PDF and Word, Please use the Catalyst Dropbox to submit your homework. You can create a digital version of your answers by directly editing the word document, or by scanning/taking pictures of your handwritten document. The final version of our submission should be in either PDF or Word. Please complete your homework in a legible manner. If we can't decrypt your handwriting, we can't grade it or give you credit for it.


Homework will be graded on both effort and correctness. If you find yourself having trouble with a problem write down what you know and how far you were able to get to get partial credit. Solutions that are correct but do not adequately explain the question may not receive full credit. Solutions that are incorrect and show no work will not receive any credit.

Late Policy

You are encouraged to collaborate with your peers. However, each person must write up their homework assignments individually. If you need an extension, you are required to submit a Haiku explaining why you need an extension BEFORE the homework deadline. Your Haiku must strictly follow the rule 5-7-5 syllable convention. Unless you have obtained an extension, late homework is subject to a late penalty of 20 percent per day.

Q & A

If you have questions about our homework, please post it on Catalyst discussion board. and allow 48 hours for us to answer your questions. If you need quick response to your questions, please send your it to: staff_cse352_15sp at

Office hours on homework will be arranged by request. We will try to resolve your questions by discussion board and mailing list, however, you can sent a office hour request to staff mailing list if you need to discuss your questions to instructor or TAs face to face. We will also arrange group office hours when we notice major problems that needs to be addressed in homework.

Past Midterms

2013sp midterm with solutions

2012sp midterm with solutions

Past Finals

2012sp final (no solutions)

CSE352 Hardware Design and Implementation

Welcome to the webpage for CSE352 Hardware Design and Implementation for the Spring 2015 quarter. This website will be updated continuously throughout the semester so please make sure to check back frequently for assignments, laboratory documents, etc.

Please check for class e-mail frequently and subscribe to the Catalyst Discussion Board (see Discussion Board section).

Course Scheduling Information:

MWF 1:30PM-2:20PM, JHN 175

Lab Sections:
Tues. 2:30PM-5:20PM, CSE 003
Thur. 2:30PM-5:20PM, CSE 003


Joshua Smith
Email: jrs at cs washington
Office: CSE 556


Hanchuan Li (Homework): hanchuan at cs washington
Office Hours: Thursday 10-11am, CSE218

Boling Yang (Homework): bolingy at
Office Hours: Thursday 10-11am, CSE218

Edwin Prasetio (HW/Lab):edwinp3 at
Office Hours: Tuesday/Thursday in Lab 2:30pm-5:20pm, CSE003

Zerina Kapetanovic (Lab): zerinak at
Office Hours: Tuesday/Thursday in Lab 2:30pm-5:20pm, CSE003

Irene Liu (Lab): Irenecyl at
Office Hours: Tuesday/Thursday in Lab 2:30pm-5:20pm, CSE003

David Orchard (Lab): dlo9 at
Office Hours: Tuesday/Thursday in Lab 2:30pm-5:20pm, CSE003

We will cover most of the concepts in Digital Design and Computer Architecture by Harris and Harris.

Digital Design and Computer Architecture

Digital Design and Computer Architecture
David Money Harris and Sarah L. Harris
2nd Edition
ISBN-10: 0123944244
Mogan-Kaufman 2012
Digital Design and Computer Architecture 2nd Edition

The textbook is available at: Amazon
Note that the above text is second edition. Using the first edition is also okay; the reading sections however may differ in a limited number of places. If you intend to use the first edition please note the reported errata to date below:

Course Goals

  1. Understanding digital logic at the gate and switch level including combinational and sequential logic elements
  2. Understanding clocking methodologies and system timing
  3. Learning how to specify digital-logic designs and compile these into digital circuit implementations
  4. Understanding the design and implementation of processor architectures

Course Syllabus

  1. Introduction to modern digital-logic design
  2. Combinational logic
    • Switch logic and basic gates
    • Boolean algebra
    • Multilevel networks and transformations
    • Programmable logic devices
    • Delay and circuit performance
    • Case studies
  3. Sequential logic
    • Clocks and timing methodologies
    • Registers, register files and memories
    • Case studies
  4. Processor Design
    • Arithmetic circuits
    • Arithmetic and logic units
    • Register and bus structures
    • Instruction set implementation
    • Memory system
    • Pipelining
    • Interrupts, memory-mapped I/O and embedded systems concepts
  5. Computer-aided design tools for logic design
    • Schematic entry
    • Hardware-description-languages
    • Simulation and synthesis
  6. Practical topics
    • Asynchronous inputs and metastability
    • Serial and parallel communication
    • Memories: RAM and ROM
    • FPGA architectures


The course consists of the following components:

  1. Lectures: There will be about 30 lectures. Attendance and participation is expected at all of them.
  2. Laboratory Assignments: The lab assignments will be the focus of the course work and will be where you learn the CAD tools and put together your processor. Lab assignments are not canned. They are open-ended design sessions that will carry over from one week to the next and you will often need more time than the 3 hour lab session to complete your work. Attendance during the scheduled lab time when the TAs are available is very important. Please come to lab prepared so that you get as much done as possible with the extra help. Laboratory assignments will be closely tied to the written homework assignments and are intended to give you a taste of working with real digital hardware. The initial set of labs are to be completed individually. We will let you know later when you may start working with a partner.
  3. Assignments: Written homework with design problems will be assigned to reinforce class concepts. Many of these will mesh with the lab assignments and will require you to use the CAD design tools.
  4. Midterm exam: The midterm exam will test your knowledge on the first half of the course. The date, length and scope is being determined.
  5. Final exam: A two-hour exam during finals week as per the University’s final exam schedule.

We will try to ensure that the workload is typical for a four-credit course, namely, nine to twelve hours per week outside of the lectures. If we do not succeed, please let us know in whichever way you feel the most comfortable (person-to-person, e-mail, anonymous feedback) and explain which parts of the course are causing you to spend too much time non-productively.

We have structured the course so that spending an hour or two per day will maximize your efficiency. You will work this way in the real world—you cannot cram a three-month design assignment into the last night—so you may as well work this way now. Plus, you will understand the material better. If you leave the homework for the day before it is due you will not have time to ask questions when (not if) the software misbehaves.

Software tools frequently consume more time then they should. We have designed the assignments to get you up to speed gradually (over the period of a few weeks), but undoubtedly there will be some start-up cost (as with any new tool). Essentially, you are learning a new language, a compiler, and getting familiar with a process. Every tool imposes a certain model. Your frustration can be high until you assimilate that model and learn to use it effectively. Be sure to use the s, and do not spend countless hours making no progress. Ask for help. Remember that these tools are written by engineers for engineers and will not necessarily conform to expectations you may have of consumer-oriented tools such as Word.


Assignments are generally due a week after being posted, at the beginning of class on the assigned due date. Homework will no longer be accepted after a solution has been published (usually within 3-4 days). If you cannot hand in an assignment in time, please email the TAs before the assignment deadline to obtain an extension. You are strongly encouraged to review the assignment solutions to ensure you understood all the problems.

Your assignments must be neat and legible. We will not spend time trying to decipher messy work. We urge you to use the graphical and word processing tools that are readily available to you in all the labs in the department. Please make good use of the schematic diagram editor in the tools you'll be using to make neat circuit diagrams to include in your assignments.


Homework assignments: Unless specifically stated otherwise, we encourage collaboration on homework, provided (1) You spend at least 15 minutes on each and every problem alone, before discussing it with others, and (2) You write up each and every problem in your own writing, using your own words, and understand the solution fully. Copying someone else's homework is cheating (see below), as is copying the homework from another source (prior year's notes, etc.). Homework assignments are your chance to practice the concepts and make sure you know them well.

Labs: Unless specifically stated otherwise, the labs are meant to be conducted individually. Make sure you go through each step individually to understand the techniques and challenges behind digital systems design. The final labs on the microprocessor design will be conducted in groups.

Grading (may be revised)

  • Midterm: 15%
  • Final: 35%
  • HW: 10%
  • Labs: 40%
  • Cheating

    Cheating is a very serious offense. If you are caught cheating, you can expect a failing grade and initiation of a cheating case in the University system. If you feel that you are having a problem with the material, or don't have time to finish an assignment, or have any number of other reasons to cheat, then talk with the instructor. Just don't cheat.

    To avoid creating situations where copying can arise, never e-mail or post your solution files. You can post general questions about interpretation and tool use but limit your comments to these categories. If in doubt about what might constitute cheating, send the instructor email describing the situation.

    Click here for Catalyst discussion board. Everyone registered for the course is automatically enrolled. You may wish to enable email notifications. This board will be used for important announcements regarding homework, exams, sections, office hours, etc.

    The Dropbox page is accessible HERE.

    Grade book is HERE .


    Read Active-HDL Tutorials in the left list for each lab
    Chip Map Reference
    Another Chipmap
    Lab 1
    Lab 2
    Lab 3
    Lab 4
    Lab 5
    Lab 6
    Lab 7
    Due date (see calendar) (@5:20pm)

    Lab Submission Policy

    Labs will be checked off in each lab sections(for student who registers lab section AA should be checked off in Tuesday section, for student who registers lab section AB should be checked off in Thurday section). Please be prepared when asking for a check off since there may be other students waiting for check off or help in the lab. You are free to attend either lab section but not for check off, if there are not enough workstations to accomodate everyone, those who are enrolled in the section will be granted priority to the workstations.

    Late lab check offs are subject to a 20% late penalty. The final lab assignments towards the end of the class may not be turned in late. The final due date for all lab assignment checkoffs is the last scheduled lab section. Beyond that date, all incomplete checkoffs will receive a score of 0.


    We will be using the Dell PCs located in the Baxter Computer Engineering Laboratory, CSE 003. Please do not eat or drink in the laboratory, and respect both the equipment and your fellow students.

    Logic Design Tools

    We will be using Active-HDL from Aldec Inc. This tool combines schematics, the Verilog harware description language and simulation into one package. This tool will allow us to design at different levels of abstraction and interfaces to a variety of implementation tools for FPGAs and ASICs. We will be using the Aldec tools for CSE467 and CSE477, so learning it in CSE352 will be valuable for future classes.

    Active-HDL from Aldec is installed in the Baxter Laboratory. We will be giving you tutorials for learning Active-HDL. These will be sufficient for this class, but you may want to check out the online documentation as well.

    Remote Access

    Active-HDL and Quartus are available outside of the 003 laboratory only for students currently enrolled in CSE352. It utilizes a license server on campus so your machine will require reasonable Internet access when you are using the tool. However, we have a limited number of concurrent licenses for this software. It is EXTREMELY IMPORTANT that if you use Active-HDL at home you completely shut down the applications when you are not actively using it so that the license is released for others to use. If you do not, and we have difficulty getting everyone access to the tool because of this, then we will have to limit home use.

    If you understand this usage model and are willing to cooperate in making sure that the most students possible can make effective use of the tool, then you can find download instructions here.

    Tutorial 0
    Tutorial 1
    Tutorial 2
    Tutorial 3
    Tutorial 4

    Read tips and hints.
    How to work from home.