September | ||||
Monday | Tuesday | Wednesday | Thursday | Friday |
26 | 27 | 28
13:30-14:20 Lecture
JHN 111 Course Overview and Logistics |
29 | 30
11:00-12:00 OH (ce)
CSE 590
13:30-14:20 Lecture
JHN 111 Review of Boolean algebra & logic gates, addition H&H p. 3-16, 20-21, 51-60 |
October | ||||
Monday | Tuesday | Wednesday | Thursday | Friday |
03
13:30-14:20 Lecture
JHN 111 CMOS logic and the digital abstraction H&H p. 16-19, 22-25, 28-32
14:30-15:30 OH (ce)
CSE 590 |
04 | 05
13:30-14:20 Lecture
JHN 111 Complex logic functions, multiplexers, decoders. H&H p. 62-68, 79-84 |
06 | 07
11:00-12:00 OH (ce)
CSE 590
13:30-14:20 Lecture
JHN 111 Combinational logic details, timing. H&H p. 69-71, 84-88
14:05-14:20 15min Quiz
|
10
13:30-14:20 Lecture
JHN 111 Carry-lookahead adder H&H Ch 5.2.1-5.2.2 + in-class notes
14:30-15:30 OH (ce)
CSE 590 |
11
09:30-12:20 Lab
CSE 003 Lab 2: Hierachical circuits. Multiplexers and reconfigurable functions. Lab2: Writeup |
12
13:30-14:20 Lecture
JHN 111 Edge-triggered registers and clocked circuits. H&H Ch 3.2.3-3.2.6 + in-class notes |
13
14:30-17:20 Lab
CSE 003 Lab 2: Hierachical circuits. Multiplexers and reconfigurable functions. Lab2: Writeup |
14
11:00-12:00 OH (ce)
CSE 590
13:30-14:20 Lecture
JHN 111 Shift-registers and system timing. H&H Ch 3.2.3-3.2.6 + in-class notes.
14:05-14:20 15min Quiz
|
17
13:30-14:20 Lecture
JHN 111 Sequential circuits. RTL abstraction. H&H Ch 3.3 in-class notes.
14:30-15:30 OH (ce)
CSE 590 |
18 | 19
13:30-14:20 Lecture
JHN 111 Register file design, simple "processor". In-class notes. |
20 | 21
11:00-12:00 OH (ce)
CSE 590
13:30-14:20 Lecture
JHN 111 Register timing constraints and circuit performance. H&H Ch 3.3, 3.5.1-3.5.2
14:05-14:20 15min Quiz
|
24
13:30-14:20 Lecture
JHN 111 Verilog for combinational & sequential circuits. H&H Ch 4.1-4.4
14:30-15:30 OH (ce)
CSE 590 |
25
09:30-12:20 Lab
CSE 003 Lab 4: Verilog, sequential circuits. Compiling/running circuits on the FPGA Lab 4 Writeup |
26
13:30-14:20 Lecture
JHN 111 Instruction Set Design. B&O Ch 4-4.1.4 |
27
14:30-17:20 Lab
CSE 003 Lab 4: Verilog, sequential circuits. Compiling/running circuits on the FPGA Lab 4 Writeup |
28
11:00-12:00 OH (ce)
CSE 590
13:30-14:20 Lecture
JHN 111 Instruction Set Design. B&O Ch 4.1.5-4.1.6
14:05-14:20 15min Quiz
|
31
13:30-14:20 Lecture
JHN 111 In Lab - Using the Y86 simulator : confer.uw.edu/circuitcircus B&O Ch 4.1.5-4.1.6
14:30-15:30 OH (ce)
CSE 590 |
01
09:30-12:20 Lab
CSE 003 Lab 5: Y86 version 1. MOV and ALU instructions. Y86 ISA simulator. Lab 5 Writeup |
02 | 03
14:30-17:20 Lab
CSE 003 Lab 5: Y86 version 1. MOV and ALU instructions. Y86 ISA simulator. Lab 5 Writeup |
04
11:00-12:00 OH (ce)
CSE 590
13:30-14:20 Lecture
JHN 111 Y86 subroutines/stack frame. B&O Ch 3.7
14:05-14:20 15min Quiz
|
November | ||||
Monday | Tuesday | Wednesday | Thursday | Friday |
07
14:30-15:30 OH (ce)
CSE 590 |
08 | 09 | 10 | 11
Veterans Day
|
14
14:30-15:30 OH (ce)
CSE 590 |
15 | 16 | 17 | 18
11:00-12:00 OH (ce)
CSE 590
13:30-14:20 Lecture
JHN 111 Y86e embedded extensions
14:05-14:20 15min Quiz
|
21
14:30-15:30 OH (ce)
CSE 590 |
22
09:30-12:20 Lab
CSE 003 Catchup day. |
23 | 24
Thanksgiving
|
25
Thanksgiving
|
28
14:30-15:30 OH (ce)
CSE 590 |
29
09:30-12:20 Lab
CSE 003 Y86 Embedded Extensions. Memory-mapped I/O, timers, interrupts. |
30 | 01
14:30-17:20 Lab
CSE 003 Y86 Embedded Extensions. Memory-mapped I/O, timers, interrupts. |
02
11:00-12:00 OH (ce)
CSE 590
14:05-14:20 15min Quiz
|
December | ||||
Monday | Tuesday | Wednesday | Thursday | Friday |
05
14:30-15:30 OH (ce)
CSE 590 |
06
09:30-12:20 Lab
CSE 003 Final project. |
07 | 08
14:30-17:20 Lab
CSE 003 Final project. |
09
11:00-12:00 OH (ce)
CSE 590
13:30-14:20 Lecture
JHN 111 Review |
12
14:30-16:20 Final exam
|
13 | 14 | 15 | 16 |