CSE 351: The Hardware/Software Interface

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Homework 3: Cache Organization and Indexing

Assigned Friday, February 13th, 2015
Due Date Friday, February 20th, 2015 at 5:00pm
Submissions Submit a PDF file of your solutions here.

Introduction

The purpose of written homework assignments is to get you thinking about the topics being covered in lecture and in readings in the textbook which are not represented in the hands-on, programming lab assignments. These written assignments also better prepare you for course examinations. It is worth noting that the book contains many practice problems similar to the problems we ask on these written assignments. The solutions for those practice problems are located at the end of each chapter and should give you a feel for the kind of answers we expect you to turn in for these kind of assignments.

Logistics

Since these written homeworks are not programming lab assignments, you will turn in your assignment online as electronic documents in PDF format. We will not accept any paper submissions.

Grading

Same rules as for homework #1 & 2

We will provide solutions to all of the problems in the written homework assignments in a timely fashion after the assignment is due. This may be around 4 or 5 days after the due date, in general, because a student may use up to 3 late days on an assignment.

Questions

Answer the following problems from the textbook. Notice that several of these problems are practice problems. If a practice problem is listed, try to solve the problem on your own first, then check your answer at the end of the chapter. Make sure you understand the solution provided, then complete the additional questions we ask about the practice problem below. Your write-up only needs to contain the information necessary to understand your answer to the *additional questions listed here* - you do NOT need to turn in the answer to the practice problem in its entirety.

  1. Practice Problem 6.10, p. 598. Repeat this problem for the following two real caches: Intel Xeon L1 data cache: m = 38, C = 32768, B = 64, E = 8. AMD Opteron 6168 L2 unified cache: m = 48, C = 524288, B = 64, E = 16.
  2. Practice Problem 6.11, p. 605. Assume that instead our cache is 2-way set associative. That is, C=64, S=2, E=2, B=16. So our cache is twice as big, and each set now contains two lines. Please give a separate answer for each of these two scenarios: a) What will the overall *miss rate* be for the original layout of the two arrays in this cache (include all accesses to array x and array y)? b) What will the overall *miss rate* be for the padded version?
  3. Practice Problem 6.12. Explain why it is NOT a good idea to use the high-order bits of the address as the set index.
  4. Practice Problems 6.13-6.17, p. 609-611. (Nothing required for turn-in.)
  5. Homework Problem 6.29, p. 632. Be sure to review and completely understand Practice Problems 6.13 - 6.17 before working on this problem.
  6. Homework Problem 6.30, p. 633. Be sure to review and completely understand Practice Problems 6.13 - 6.17 before working on this problem.
  7. Homework Problem 6.39, p. 637.

Notes

Make sure you are using the 2nd edition of Computer Systems: A Programmer's Perspective, ISBN: 978-0-13-610804-7. If you're not using the right book, you might be doing the wrong problems!

Submitting Your Work

Please turn in a PDF file containing your answers to the Catalyst Drop Box for this assignment. We will not accept submissions that are not in PDF format.