# Author: Hannah C. Tang (hctang@cs)
#
# Makefile for Homework 5


	### Variables ###

CXX = /uns/bin/g++-3.0.3  # The standard g++ compiler is broken
CXXFLAGS = -Wall -ansi -g # Always compile with these flags
TARGET_NAMES = bst-test   # You can add more targets here


	### Rules ###

# The first target in a Makefile is the default.  That is, a simple "make"
# at the command line will build the "all" target for this Makefile.  
# Remember the general syntax for rules in a Makefile is:
# <target> : <dependancies>
#	<command1 to generate target>
#	<command2 to generate target>
#	  ...
#	<commandn to generate target>




### This makes everything -- currently, only one executable
### (but there can be more)
all : $(TARGET_NAMES)




### These rules make the bst-test program

# This executable depends on object code generated from bst-test.cc and
#  the templated code generated by the instantiation file.  This line
#  builds (but does not compile) the executable.
# The $@ variable is the name of the target; the $^ variable is 
#  list of all the dependancies.
bst-test : bst-test.o TemplateInst.o
	$(CXX) $(CXXFLAGS) -o $@ $^

# This line compiles/generates the object code.  It does not actually 
#  build the executable (see above for the build line) The $< variable 
#  is the name of the *first* dependancy
bst-test.o : bst-test.cc BinarySearchTree.hh BSTNode.hh
	$(CXX) $(CXXFLAGS) -c $<



### If you plan on building more than one executable, add those rules here




### This rule compiles object code for *all* the templated classes

#  How does it do this?  Well, because we are using *forced*
#  (aka "explicit") template instantiation, all of the relevant
#  templated code (.cc's) are #included into the TemplateInst.cc file.
#  So compiling this file is equivalent to compiling all the templated
#  files.  Note that it is *not* necessary (in fact, it is incorrect!)
#  to compile the templated files seperately 
TemplateInst.o : TemplateInst.cc BinarySearchTree.hh BinarySearchTree.cc BSTNode.hh BSTNode.cc
	$(CXX) $(CXXFLAGS) -c $<



# This rule is a fake target -- that is, it doesn't generate any object
# files; rather, the make command will execute the following rm command
# (which cleans out object files, emacs backups, core files, and 
# your executable).
clean :
	rm -f *.o *~ core $(TARGET_NAMES)


# And .... as a reward for reading through this entire Makefile, here is
# is some information on pattern rules!  =)
# 
# Quoth Evgeny Roubinchtein (evgenyr@cs.washington.edu):
#
# > You could also use "patten rules" to tell 'make' how to produce a
# > .o given a .cc.  You wouldn't then have to write rules like:
# >
# > FOO.o : FOO.cc
# >        $(CXX) $(CXXFLAGS) -o $@ $^
# >
# > for each .o you want to produce.
# >
# > Often, people also use automatic dependency generation with pattern
# > rules.  The sample Makefile Justin Husted has written (in /uns/examples)
# > uses pattern rules and automatic dependency generation.
# >
# > Pattern rules are documented here:
# >  http://www.gnu.org/manual/make-3.79.1/html_node/make_100.html#IDX828
# >
# > Automatic dependency generation is documented here:
# >  http://www.gnu.org/manual/make-3.79.1/html_node/make_44.html#IDX259
#
# Thanks, Evgeny!