####      Generic Makefile      ####

# What is "make", you might ask?  Well, the purpose of the "make" utility
# is to automatically determine which pieces of a large program need
# need to be recompiled, and to issue the appropriate commands to 
# recompile them.
#
# To use "make", you must write a file called a "Makefile" which describes
# the relationships among files in your program, and states the commands
# for updating each file.  For example, typically the executable is
# updated from object files, which are in turn made by compiling source
# files.  Given a list of your source files, the "make" tool will 
# automatically detect these relationships for you.
#
# The long and short of it, however, is that typing "make" at the 
# command prompt will compile your program for you.  =)  You only
# need to modify the SOURCES variable so that it lists all your .cc 
# files.  Also, you may want to modify the TARGET variable to be the
# name of the resulting executeable.



### Variables -- you may wish to change some of these ###

CXX = /uns/bin/uns-g++
CXXFLAGS = -Wall -ansi -g 	# Always compile with these flags
TARGET = target   		# The name of your executeable
LDFLAGS =			# You can put linker options here

#  The following is just a list of your source files. Don't split the lines
#  unless you escape the newline with a \.  
SOURCES = test.cc



### Rules -- you probably don't want to change these  ###

# The first target in a Makefile is the default.  That is, a simple "make"
# at the command line will build the "all" target for this Makefile.  
# Remember the general syntax for rules in a Makefile is:
# <target> : <all file dependencies>
#	<command1 to generate target>
#	<command2 to generate target>
#	  ...
#	<commandn to generate target>
#
# You must have a single tab (not space!) infront of each command.
# These rules are used to override the defaults.  By default, the make
# program will try to compile your code according to the values of some
# built in variables.  For C++, the variables that matter are CXX, and
# CXXFLAGS.  For linking, LDFLAGS changes the default behaviour.  You
# really only want to add in your own rules if the defaults don't suit you.


## This makes everything (in this case, only one target)
all : $(TARGET)


## This rule makes the "clean" target

# This rule is a fake target -- that is, it doesn't generate any object
# files; rather, the make command will execute the following rm command
# (which cleans out your old object files and executable).
#
# The .PHONEY ensures that make knows this target is fake
.PHONEY: clean
clean :
	rm -f *.o *.d $(TARGET)


## These rules make the reverse program

# This executable depends on object code generated from reverse.cc and
#  stack.cc.  This line links (but does not compile) the executable.
# The $@ variable is the name of the target; the $^ variable is a 
#  list of all the dependancies
$(TARGET) : $(SOURCES:%.cc=%.o)
	$(CXX) $(LDFLAGS) -o $@ $^


# These are the automatic dependency rules which tells gcc/g++ to figure
# out the dependencies of each source file, and places these dependancies
# in a corresponding .d file.
%.d: %.cpp
	$(SHELL) -ec '$(CXX) -MM $(CXXFLAGS) $< \
	| sed '\''s/\($*\)\.o[ :]*/\1.o $@ : /g'\'' > $@; \
	[ -s $@ ] || rm -f $@'

%.d: %.cc
	$(SHELL) -ec '$(CXX) -MM $(CXXFLAGS) $< \
	| sed '\''s/\($*\)\.o[ :]*/\1.o $@ : /g'\'' > $@; \
	[ -s $@ ] || rm -f $@'

%.d: %.c
	$(SHELL) -ec '$(CC) -MM $(CCFLAGS) $< \
	| sed '\''s/\($*\)\.o[ :]*/\1.o $@ : /g'\'' > $@; \
	[ -s $@ ] || rm -f $@'


# This line includes the automatically generated makefile rules
# (located in the .d files); that is, it makes this Makefile aware
# of your program's dependancies
include $(SOURCES:.cc=.d)