Lecture Notes for Week 4:
Given an RTL model, the objective of logic synthesis is to find a structural model, using elements from a “cell library”, that matches the RTL timing at the state transitions. The contents of the registers in an RTL model should match the contents of the registers in the synthesized structural model. Since the RTL registers map directly to structural registers, the primary purpose of logic synthesis is to optimize the combination logic portion of the system. So, for the remainder of these notes, we ignore the registers and treat everything as combinational logic.
Thus, problem of logic synthesis is to:
1. Convert a text representation of the combinational logic portion of an RTL model (such as Verilog or Handel-C) into an internal representation that can be easily manipulated
2. Optimize the internal representation against some technology independent measure of quality, such as the number of nodes in a tree, depth of the expression, etc.
3. Map the internal representation to a given cell library while minimizing the amount of cell area/power or combinational delay of the circuit.
Give the function F=a+bc, one possible internal representation is an operator tree as in:
While the operator tree may seem to be convenient, it has several undesirable properties:
1. It is difficult to tell if two functions (or sub-expressions of a single function) are identical. For example, if we define G=(a+b)(a+c) and H=G+F, then by the distributive law of boolean algebra, we know that F=G, and therefore, that H=F (or H=G). Which means that we can choose not to implement either F or G. This is an example of a technology independent optimization that we would want to be able to do. However, this operator tree representation does not lend itself to finding common sub-expressions. See the complete operator tree for H below.
Using this representation format, there is no easy way for the logic synthesis algorithm to determine that F=G. If both of these trees appear as sub-trees of a larger function, then we might synthesize enough hardware to implement the function twice.
2. Another problem is that it is difficult to recognize when one function is the complement if another. This is important to know for several reasons. Suppose X = !Y. The operator trees for Z = X+Y and W = XY might be very large, but in fact Z = 1 and W = 0. We need no logic at all to implement them. Ideally, our internal representation will make it easy to determine both Tautology (always 1) and Not-Satisfiable (always 0). A system with this property would also make it easy to prove that two functions are the same for the purpose of formal verification.
ROBDD
There is a representation form called ROBDD (reduced, ordered, binary decision diagram) that has these two critical properties. ROBDD is a special form of a BDD. Each node of a BDD can be though of as a multiplexor. The output of a node is the “low” edge input if the variable associated with that node is 0, and it is the high edge input if the variable associated with that node is 1. For example, the BDD for the function F=a is represented by a BDD as:
Likewise, F’ can be obtained by swapping the 0 and 1 nodes at the bottom of the tree as in:
Since the BDD can be thought of as a tree of multiplexors, we can obtain a BDD expression of any function by recursively applying Shannon expansion. For example the function F = a+bc expands (over ‘a’) to the function F = a[1] + a’[bc]. If we apply expansion now with respect to ‘b’, we get F = a[1] + a’[b[c] + b’[0]]. Thus, the BDD form of F can be represented as:
A BDD will be ordered (OBDD) if we apply expansion in the same variable order in all branches of recursion. A OBDD has the property that any path from a leaf node to the output will encounter input variable nodes in the same order (though not all paths will have all nodes). The above representation of F=a+bc is ordered, and it also happens to be reduced. An OBDD is reduced (ROBDD) if it has no redundant nodes (both high and low edges of a node point to the same node) and no duplicate nodes (two nodes who’s high edges point to the same node, and who’s low edges point to the same node). The examples above are already reduced. To learn more about reducing a BDD (a procedure that is linear with respect to the number of nodes in the graph), see either of the references below.
A great property of ROBDD’s is that if two functions are the same, their ROBDD representations will be isomorphic (the same) if their variable orderings are the same. For example, if we expand G=(a+b)(a+c) over ‘a’, we get G = a[1]+a’[bc] which is the same as the expansion over ‘a’ of the original function. A consequence of this propery is that if we a build an ROBDD for H=F+G we will simply get the same ROBDD as we would for either F or G alone. We are guaranteed never to unwittingly implement redundant sub-expressions of a function.
Another great property of ROBDD’s is that it is easy to find sub-expressions that are complementary. If two nodes are complementary, then the low edge of one node will point to the same node as the high edge of the other, and the high edge of the first node will point to the same node as the low edge of the other. As in the following BDD
In a BDD, a special arc (shown as a double arrow) can be added between complementary nodes so that they are easy to find later.
Finally, the ROBDD for any function that evaluates to 1 will always be the single node ‘1’, and the ROBDD for any function that evaluates to 0 will always be the single node 0. Therefore we won’t waste any logic implementing such functions.
It is important to note that the size (number of nodes) of a ROBDD is dependent on the ordering chosen. If we expand F in the order b-a-c instead of a-b-c, we get the following expression;
F = b[a+c] + b’[a] = F = b[a[1]+a’[c]] + b’[a[1]+a’[0]] = b[a[1]+a’[c[1]+c’[0]]] + b’[a[1]+a’[0]]
which is the following ROBDD:
Notice that this ordering produces a larger ROBDD. Of course, logic optimization is an NP-Complete problem. This fact shows up in the fact that an ROBDD on n variables may have an exponential number of nodes. Fortunately, for the vast majority of logic functions, it is possible to find an ordering that produces a manageable number of nodes, and in fact, finding a good ordering is very closely related to the technology independent optimization problem. However, some functions, such has multiplication, do not have any orderings that are not exponential in size.
Technology Mapping
Image that we have a cell library with the following logic functions: NOT, AND, OR, and 2:1Mux. The problem of technology mapping is to use the devices in this library to implement the function represented by a BDD. There are two basics steps:
1. Draw small BDD “patterns” that correspond to the logic functions in the given cell library. For example, the logic function for NOT has the following BDD Patterns:
If either of the two patterns enclosed in loops are found in the BDD, then a NOT cell can be use to produce the function that corresponds to the circled node, and the corresponding part of the BDD enclosed by the dotted shape will be covered.
The functions AND and OR are represented by the following BDD patterns:
The basic objective of technology mapping is to cover the entire BDD with patterns from a given cell library, while optimizing area/performance/cost measures.
For F=a+bc, here is a covering of the ROBDD of Fon the order (a,b,c) that corresponds to the expression F = a + bc.
For a hypothetical FPGA made up ACT-1 cells, the pattern library would include those above along with several hundred other possibilities. Two of the other possibilities in the ACT-1 library are XOR and XNOR functions. Which one we use depends on which edge of ‘x’ is available, if the inputs to the hi side are available then we would need the XNOR function (F = X xnor H). Likewise, if the inputs to the low side are available then we would use an XOR and implement F = X xor H.
This library can be used to cover the ROBDD of a full-adder, on the order (c,a,b). We put ‘c’ first because we want ‘c’ to be the last input to our function, shortening the critical path.
A Covering for this graph from the library (NOT, AND, OR, XOR, XNOR, 2:1mux) is:
Notice that since the XOR function requires only the un-inverted input, the complements, B’ and (AxorB)’, aren’t included in the covering. The covering corresponds directly to an implementation in the given library.
Sources:
Henrik Reif Andersen, Introduction to Binary Decision Diagrams, Lecture Notes from Web at http://www.it.dtu.dk/~hra, Department of Information Technology, Technical University of Denmark
S. Devadas, A. Ghosh, K. Keutzer, Logic Synthesis, McGraw Hill Series on Computer Engineering, 1994