# ======================================================================================
# User Contraint File
# This file contains all the constraints defined by the user.
# The two types of constraints include 1) pin assigments and 2) net delay constraints.
#
# Below contains pin assignments for several nets. If you made changes to this file
# without changing your design, you must delete the previous implementation version in # order to have the changes to take effect.
You can delete the version from the# project->delete version in the project manager.
#
# Xillinx Foundation has provide an interface for editing net delay constraints. Thus,
# these constraints will not be in this file and we could avoid messing with the syntax.
# If you choose to edit your net delay constraints in this file, refer to on-line
# documentation. (There should be a link from the start menu on your desktop.)
# =======================================================================================
# "NET", "LOC" are keywords.
# "CLK", "LED0" are the names given to any net in your schematic.
# "Pxx" means the pin numbered xx.
# ===== ON CHIP CLOCK ==========
# Pin 13 is the on-chip clock
NET CLK LOC=P13;
# 1
# 0 |6| 2
# 5 |_| 3
# 4
# ===== LED DRIVER OUTPUTS =====
NET LED0 LOC=P26;
NET LED1 LOC=P25;
NET LED2 LOC=P24;
NET LED3 LOC=P18;
NET LED4 LOC=P19;
NET LED5 LOC=P23;
NET LED6 LOC=P20;