CSE 585 Lab 1

CSE 585 Lab 1

Overview

The purpose of this lab is to become familiar with the tools and have hands-on experience with lecture materials. We will be using the Xilinx Foundation as the tool for digital system design in the first phase of the class. Your design will be implemented on a prototyping system that uses a Xilnx XC4000XL family FPGA. The prototyping system provides you with a 12MHz clock signal, a device programming interface, and on board single digit 7-segment display (which is sufficient for BITS results). See the end of this file for turn-in requirements.

Equipment

1) Xess board - Xillinx XC4000XL board.

2) Protoboard

3) 2 power supplies (one for the protoboard and one for the Xess Board )

4) Dip switches and resistors

5) wires and other tools

Below is a guide to using the Xilinx Foundation tool suite. The Foundation tool suite is a mini version of the ASIC design flow that we discussed in lecture last week. It starts with design capture in the form of schematics, state diagrams, and Verilog code. Once you've captured your design, you can simulate it using a "simulation script" language supported by the Foundation environment. Unfortunately, unlike Verilogger, the "test" program cannot be written in Verilog, you have to use the Xilinx script language. The results of simulation are available as simulation waveforms in a graphics window.

One you verify your circuit for functionality, the Foundation suite can be used to compile the design into a "bit" program for the FPGA device on the Xess board. The compilation process does several things: it maps the design entry information to "CLBs" available on the FPGA (we will get into that in more detail later); it "places and routes" the mapped devices, computes the actual delay characteristics of the design, and writes out a "bit" sequence for programming the FPGA. Before testing your program in hardware, it is probably a good idea to a) rerun the simulation using "back annotated" timing from the implementation and b) take a look at the the results of static timing analysis to see if what your minimum clock period can be, and what the I/O timing requirements are. Finally, you can download your design to the prototype system and run it in real time. If you have a chance, you might want to hook up a scope to see how the actual timing corresponds to the results reported by the tools.

In addition to this lab guide, there is also an on-line documentation and tutorial available. You should find the link from the start menu on the desktop.

Start the Xilinx Foundation Tools from the start menu.

Under the file menu choose to "Restore Project" from the archive located in \\Ifilesrv1\courses\cse585\init.zip. You should restore this project to your local machine while you are working on the project (the desktop is fine). If you want to move a project that is already open, choose File-Copy Project.

Schematic Based Design:

To get started with schematics, select the Schematic Editor from the project manager to get a blank sheet for entering your design. There is a couple of buttons on your left which allows you to enter your design. Click here for a menu.

Creating a block for hierarchical design.

1) If your block is to contain schematic information

After you have entered your design for a box, select Hierarchy->Create Macro Symbol From Current Sheet from your menu bar. Your logic box will be entered into the project library and be available from the Symbols Tool Box.

2) If your block is to contain a Verilog model

From your schematic editor menu select Tools->Symbol Wizard and follow the wizard. In the same dialog box for entering the Symbol Name, select HDL code for content and select Verilog as the HDL language. Enter the input and ouput pins necessary by clicking the "New" button. Choose name, pin direction etc as desire. Don't worry if you don't know exactly what pins you will need. You can always modify the pins through the HDL editor as you enter you design. Again, this new box will be entered into the project library and be available from the Symbols Tool Box. From the schematic editor, select the "Hierarchy" button and click on the box to bring up the HDL editor for the box. After you have entered your design, compile your design by selecting Synthesis->Synthesis from the HDL editor menu. Check for errors and warnings. (You may find the errors and warnings listed on the project manager.). You can just close the HDL editor and the system will ask you if you want to re-compile it.

When entering your design observe the following rules (this has already been done for you for this project).

All input pins have to go through an IPAD then an IBUF.

All output pins have to go through an OPAD then an OBUF.

For system clock signal, use a BUFG instead of a IBUF.

These could be found in the Symbols Tool Box.

Verifying your Design

You can simulate your design using the Logic Simulator. Select Functional Simulation from your project manager. Select Tools->Script Editor and choose "empty script" to edit your simulation script ( .cmd file). Click here for a sample script. To start simulation, select File->Run Script File and choose a.cmd file. See here for an example simulation script that is much more complex than you need, but it shows all of the features of the language.

You will notice from the waveform that everything happens right at the clock edge. No delays is incorporated into the simulation. Signal delays could be simulated after implementation of design by using the Timing Simulation. (The Timing Simulation uses the same test script as the Functional Simulation.)

User Constraints

In general, there will be 2 types of user constraints, 1) pin assignments and 2) net delay constraints. You could choose to edit them into the .ucf file or use the Constraint Editor as a tool. (select Tools->Implementation->Constraints Editor to open the editor). Refer to "Using the Constraint Editor" section from the on-line documentation for details. You can find the .ucf file which contains some pin assignments here. Use pin 27,28,29,7,8,9,14,68,72 for your dip switch (here is 9 pins, just in case you need an extra one). The INIT project also has two example PIN assignment constraints in the init.ucf file.

Design Implementation

This step would map and route your design onto the Xillinx XC4000XL board. Make sure that 4010XLPC84 is your selected device and running at speed 09. Implementation log files can be found under the Report tab in the project manager. Select Implementation from the project manager to start this phase of the design.

Timing Analysis and Timing Simulation

Select Timing Analysis from the project manager then Analysis from the menu for detail analysis of your design. You can also perform post synthesis simulation using the original script along with real timing data from the implementation.

Connecting the XESS Board and the Protoboard

IMPORTANT: MAKE SURE THE XESS BOARD AND THE PROTOBOARD HAS A COMMON GROUND. Pin 52 on the XESS board is the GND of the board. Connect that pin to the ground of your protoboard before wiring anything. Double check before powering up the 2 boards. Each of the boards has their own power supply. Implement your input DIP switches.

Downloading your Design

Before downloading, simulate your design for correctness and check for errors and warnings.

Connect your XESS board to your PC through a parallel cable. A bitstream of the design, created, during the implementation phase, will be downloaded through the parallel port using the program "xsload". The bitstream (.bit file) is located in your directory with the same name as your project. Run "xsload" (located at d:\xstools\bin) with the .bit file as the argument in command prompt. If everything goes well, you will see ' * ' during download and your design will be loaded onto the board and will immediately start running.

Note:

When copying the project, use File->Copy Project instead of drag and drop. This ensures a proper and complete transfer of the entire workspace. Each project workspace is associated with a .PDF file which is located one level above the project directory. The Xillinx Project Manager won't be able to launch your project without it. So, if you really have to use drag and drop, make sure you copy this file too. This will work most of the time but no guarantee.

Please turn in the following information:

The members of your lab group
Your final sequential system (including Verilog and Schematic)
Your final combinational system (including Verilog and Schematic)

For the combinational and sequential implementations turn in:

The reported setup time for DATA (the smaller the better)
The reported CLK to BITS delay time. This tells a receiver of BITS how much time they have to process bits before the results must be stored.
The total number of CLBs used to program the device
The reported minimum clock period of the design
The reported delay from new DATA to BITS and to LEDs (you will have to do some math for the sequential case)
The measured delay from new DATA to LEDs.

Please record all of this data during lab, then appoint a member of your group to clean it up it up a send it to me by Monday 1/24.