Solution to Assignment 3

1. Block Diagram

CAM Synch: This block synchronizes data between the Camera’s clock domain and the clock domain of the system. Pixel data is multiplexed onto the four input data lines. On the rising edge of the clock, the most significant 4 bits of pixel data are valid, and on the falling edge the least significant 4 bits are valid. These values are latched into data registers using the camera’s clock, then are sampled by the system’s clock into another set of registers. The camera’s clock is also sampled at the system clock rate to determine when a new data value has arrived (after the falling edge). This like what we did to sample the DATA value in the synchronous version of BITS.

FiltIn: Responsible for storing data into memory in the correct location by keeping track of pixel addresses coming in. This block converts the input form 356x292 pixel image to a 256x256 image and aligns data in the FIFO with the proper address. FiltIn watches the input Frame Reset from the camera to determine when a new image is coming (resets row and column address counters). This block also keeps track of which block of memory is currently being used for input data. Double buffering is supported to allow an old frame to be displayed while a new frame is being loaded.

FIFO: Stores input data during times that main memory is busy reading data for display. The FIFO must be big enough to store data all of the data received from the camera during the time that a 256 byte row is being read out of memory. The 256byte row takes 20us. At a peak data rate of 3.1MB/s this would be 66bytes of input data, so a 64byte FIFO would be too small. The FIFO will easily empty out at the end of each row of output data since the blank part is 3 times as long as the used part.

Mem Control: Arbitrates access to the off-chip memory. The memory can perform one operation per cycle. The memory controller gives priority to output data reads, allowing the input data to be written when the output address is outside of the image area (blank).

SychGen: Generates the row and column addresses for the display and also generates the synch signals required by the VGA display system. Note that the horizontal and vertical address space is 527x759 of which only 256x256 is used. This is the reason that we have spare memory cycles to use for input data and possibly for other processing.

FiltOut: Performs any post processing required on the output pixel stream. In this case, FiltOut merely makes sure that blank (black) pixels are sent during the time that the address counters are out of the 256x256 image range.

2. Memory Bandwidth Utilization (Average)

Input Data

The input data rate is 356x292x30 bytes/second = 3.1MB/s

Of this, only 245x256x30 bytes are retained, for a total about 2MB/s averages sustained input data rate.

Output Data

The total output data rate = 12M Cycles/s * (256^2/527x759) (ratio of used to total pixels) = 2MB/sec

Total Average Memory Bandwidth Utilization = 4/12 = 33%

3. Memory accesses available during image loading (worst case)

Input Data

Load time = 1/30sec = 400K available memory cycles (12M/30). During that time, 65K accesses are used for incoming data (by definition, one frame worth).

Output Data

In the worst case, the output image has just started over again at address 0,0. Since each row of output is 759 cycles long, the time period will include the first 527 (400K/759) rows of the output address space, of which 256 rows will have 256 bytes of output data each for a total of 65K memory accesses.

Total

65K input + 65K output = 130K access accesses out of 400K available cycles:

Worst case spare access = 400K - 128K = 270K spare access or 32% utilization. In other words, the incoming frame rate matches the outgoing frame rate so the average utilization is the same as the worst case utilization over the duration of a frame. It will be higher at the beginning of the frame.

4. Probably the best place to put the cross hairs is in the output filter block (VGACONTROL8) by replacing the BlankPixel code with brightspot detection code and cross hair insertion. It seems as though it would also be possible to put the cross hairs into memory during input filtering, but then strange things might happen if there is some bank overlap. You would have to write the cross hairs into memory in place of the input data.

Some other effects that you might be able to implement in this FPGA: Chroma Key (monochromatic), Fade, Image Stabilization, zoom, etc.