module gen(DATA, BITS);
input [7:0] DATA;
output [3:0] BITS;

reg [3:0] BITS;
reg [7:0] tmp;

  always @(DATA) begin
    tmp = DATA;
    BITS = 0;
    while (tmp) begin
      if (tmp[0]==1) BITS = BITS + 1;
      tmp = tmp >> 1;
    end
  end
endmodule

module genSeq(DATA, BITS, PDATA, CLOCK);
input CLOCK;
input [7:0] DATA;
output [3:0] BITS;
output [7:0] PDATA;

reg [3:0] BITS;
reg [7:0] tmp;
reg [7:0] PDATA;
wire reset;

assign reset = DATA != PDATA;
initial PDATA = 0;

always @(posedge CLOCK) begin
  if (reset) begin
    PDATA = DATA;
    tmp = DATA;
    BITS = 0;
  end else begin
    if (tmp[0]) BITS = BITS + 1;
    tmp = tmp>>1;
  end
end
endmodule