Assignment 3

Lab Preparation:

Study the design data packet handed out in class and answer the following questions (we will put the packet on the web too):

1. Draw a simplified block diagram of the system (one piece of paper) and briefly describe the role of each block.

2. IF the camera is providing data at a rate of 30 frames/second and that the FPGA system clock is running at 12MHz, what is the overall memory utilization of the system (the memory can support up to 1 read or write access per cycle)? In addition to the info contained in the design data, you will also need one more data point from the camera datasheet.

3. How many unused memory accesses are there in the time it takes a single frame to be loaded from the camera?

4. Which block in the design would you replace to implement "bright spot cross-hairs" (as demo'd) if you were required to do it without adding any more memory accesses to the system. The demo version was implemented this way.

5. Write a replacement Verilog model to place crosshairs on the bright spot. Your solution should account for stray bright single pixels that might results from noise, and the cross hairs should move smoothly as the bright spot moves through the scene, or when a new brighter spot appears.

We will develop and test your ideas in lab 2.

Reading

Read Chapter 5 of Smith and do problem 5.1 (no need to turn it in). Chapters 4 and 6 are optional but useful, and we will get to Chapter 7 later next week.