CSEP548: Computer Architecture
Catalog Description: Architecture of the single-chip microprocessor: instruction set design and processor implementation (pipelining, multiple issue, speculative execution). Memory hierarchy: on-chip and off-chip caches, TLBs and their management, virtual memory from the hardware viewpoint. I/O devices and control: buses, disks, and RAIDs.
Prerequisities: (none listed) Credits: 4.0Portions of the CSEP548 web may be reprinted or adapted for academic nonprofit purposes, providing the source is accurately quoted and duly credited. The CSEP548 Web: © 1993-2024, Department of Computer Science and Engineering, University of Washington. Administrative information on CSEP548 (authentication required).