CSE 590G, Architecture Lunch

Course organizers:

Carl Ebeling Jean-Loup Baer and Susan Eggers

Meeting time:

Tuesdays, 12:30pm to 1:20pm, in Loew 114

Schedule

Week 1 (4/6):

"VLSI Architecture: Past, Present, and Future", by Dally, William J., and Lacy, Steve.
(David Ely)

Week 2 (4/13):

"A Bandwidth-Efficient Architecture for Media Processing", by Rixner, Scott., Dally, William J., ...
(Patrick Crowley)

Week 3 (4/20):

Maps: A Compiler-Managed Memory System for Raw Machines by Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
(Wayne Wong)

Week 4 (4/27):

"Architecture Design of Reconfigurable Pipelined Datapaths", D. Cronquist, et. al., Advanced Research in VLSI (ARVLSI-99).
(Michael Swift)

Week 5 (5/4):

"A High-Performance Microarchitecture with Hardware-Programmable Functional Units", Rahul Razdan and Michael Smith, Micro-27, Nov. 1994.
(Douglas Low)

Week 6 (5/11):

"Garp: A MIPS Processor with a Reconfigurable Coprocessor," by John R. Hauser and John Wawrzynek, (FCCM '97)
"Instruction Level Parallelism for Reconfigurable Computing," by Timothy J. Callahan and John Wawrzynek, (FPL'98)
(Kurt Partridge)

Week 7 (5/18):

"Impulse: Building a Smarter Memory Controller," by J.B. Carter, E.L. Brunvand, A. Davis, ...., (HPCA-99)
(Stefan Berg)

Week 8 (5/25):

"T0: A Single-Chip Vector Microprocessor with Reconfigurable Pipelines," by Krste Asanovic, et. al.
(Miguel Figueroa)

Week 9 (6/1):

"PipeRench: a Coprocessor for Streaming Multimedia Acceleration", by Seth Goldstein, Herman Schmit, ... (ISCA 1999).
(Josh Redstone)

Week 10 (6/8):

Finals week. Class does not meet.