CSE 590G Architecture Seminar
Autumn 2017 — Monday, 12:30pm — CSE 503
Theme: Spatial and Reconfigurable Architectures
Subscribe to the calendar: iCal or Google Calendar.| Date | Discussion Leader | Paper |
|---|---|---|
| Oct 2 | Everyone |
Assign Papers |
| Oct 9 | Eddie |
Fine-Grained DRAM |
| Oct 16 | Vincent |
Stream Dataflow Acceleration |
| Oct 23 | Guest: Matt Sinclair |
Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems |
| Oct 30 | Luis / Meghan |
Mallacc: Accelerating Memory Allocation |
| Nov 6 | Amrita |
Programming Heterogeneous Systems from an Image Processing DSL |
| Nov 13 | Guest: Mark Silberstein |
GAON: General-purpose Application Offload to Near-Network Processors |
| Nov 20 | Douglas |
Eyeriss: A Spatial Architecture for Energy-efficient Dataflow for Convolutional Neural Networks |
| Nov 27 | Emily |
Plasticine: A Reconfigurable Architecture for Parallel Patterns |
| Dec 4 | Jan Gray |
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Framework |
Logistics
- Traditional paper discussions in addition to discussions of perspectives or visionary talks from people in our field
- Up to 10 slides presenting work
- 2 original slides for discussion
Paper Suggestions
- Stream Dataflow Acceleration - Appears in ISCA '17
- Clank: Architectural Support for Intermittent Computation - Appears in ISCA '17
- Plasticine: A Reconfigurable Architecture for Parallel Patterns - Appears in ISCA '17
- A Pythonic Approach to Rapid Hardware Prototyping and Instrumentation - Appears in FPL '17 / GitHub link
- Reconfigurable Acceleration of Genetic Sequence Alignment: A Survey of Two Decades of Efforts - Appeares in FPL '17
- CHARSTAR: Clock Hierarchy Aware Resource Scaling in Tiled ARchitectures - Appears in ISCA '17
- Eyeriss: A Spatial Architecture for Energy-efficient Dataflow for Convolutional Neural Networks - Appears in ISCA '16
- DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric - Appears in ISCA '16
- DynaSpAM: Dynamic spatial architecture mapping using Out of Order instruction schedules - Appears in ISCA '15
- Programming Heterogeneous Systems from an Image Processing DSL
- Celerity: An Open Source RISC-V Tiered Accelerator Fabric - Appears in HotChips '17
- Specializing a Planet's Computation: ASIC Clouds - Appears in IEEE Micro Top Picks '17
- QsCores: Trading Dark Silicon for Scalable Energy Efficiency with Quasi-Specific Cores - Appears in MICRO '11
- Fine-Grained DRAM: Energy Efficient DRAM for Extreme Bandwidth Systems - Appears in MICRO '17