CSE590G: Architecture Seminar, Spring 2011

Mondays, 14:30-15:30, Room CSE503.

A discussion leader does not need to prepare a full presentation, just 2-3 slides with the summary and discussion points. Focus on what we should all think about!

DateDiscussion LeaderPaper
March 28 Luis Organizational Meeting, paper assignments
April 4 Sam King (UIUC) talk. Title/Abstract TBD.
April 11 Hadi, Rodolfo Case for Neuromorphic ISAs
April 18 Emily, Joe The ZCache: Decoupling Ways and Associativity
April 25 Seungyeop, BrandonM MAUI: Making Smartphones Last Longer with Code Offload
May 2 Stephen, Andrew Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU
May 9 Franzi, MarkZ Cycles, Cells and Platters: An Empirical Analysis of Hardware Failures on a Million Consumer PCs
May 16 Tom, Katelin From Microprocessors to Nanostores: Rethinking Data-Centric Systems
May 23 Jacob, Adrian Exploiting Half-wits: Smarter Storage for Low-Power Devices
May 30 --- Memorial day.


Here is the list of papers to choose from. Email luisceze if you have any questions, suggestions or complaints. We can also use the mailing list.
  1. From Microprocessors to Nanostores: Rethinking Data-Centric Systems, IEEE Computer Jan'11.

  2. Google-Wide Profiling: A Continuous Profiling Infrastructure For Data Centers, IEEE Micro, Jul 2010.

  3. Power-Aware Computing with Dynamic Knobs, ASPLOS'11.

  4. Improving Software Diagnosability via Log Enhancement, ASPLOS'11.

  5. A Case for Neuromorphic ISAs, ASPLOS'11.

  6. Cycles, Cells and Platters: An Empirical Analysis of Hardware Failures on a Million Consumer PCs , EuroSys'11.

  7. MAUI: Making Smartphones Last Longer with Code Offload, MobiSys'10.

  8. Exploiting Half-wits: Smarter Storage for Low-Power Devices, FAST'11.

    9.
  9. Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU, ISCA'10.

    10.
  10. The ZCache: Decoupling Ways and Associativity, MICRO 2010.

    11.
  11. ReMAP: A Reconfigurable Heterogeneous Multicore Architecture, MICRO 2010.

  12. The virtual write queue: coordinating DRAM and last-level cache policies, ISCA 2010.

  13. Cohesion: A Hybrid Memory Model for Accelerators, ISCA 2010.