Date	Presenter	Paper
Jan 6th	Done
Jan 13th	Andrew Petersen	Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation Dan Ernst, Nam Sung Kim, Sanjay Pant, Shidhartha Das, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, University of Michigan; Krisztian Flautner, ARM Ltd.; Trevor Mudge, University of Michigan.
Jan 20th	Steven Swanson	Microarchitectural Exploration with Liberty Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, and David I. August (Princeton University)
Jan 27th	Andrew Putnam	TLC: Transmission Line Caches Bradford M. Beckmann, David A. Wood, University of Wisconsin-Madison.
Feb 3rd	Andrew Schwerin	Using Interaction Costs for Microarchitectural Bottleneck Analysis Brian A. Fields, Rastislav Bodik, University of California-Berkeley; Mark D. Hill, University of Wisconsin-Madison; Chris J. Newburn,Intel.
Feb 10th	Martha Mercaldi	A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor Shubhendu S. Mukherjee, Christopher T. Weaver, Joel Emer, Intel Corporation; Steven K. Reinhardt, Intel Corporation and University of Michigan; Todd Austin, University of Michigan.
Feb 17th(ISCA decision 17th)
Feb 24th	Sam	Run-time Power Monitoring in High-End Processors: Methodology and Empirical Data Canturk Isci, Margaret Martonosi, Princeton University.
Mar 2nd	Rick Cox	Isca paper to be named later
Mar 9th	Doug Lowe	Isca paper to be named later