CSE590G: Architecture Seminar, Autumn 2004

Papers this term:

• Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams
• Transactional Memory Coherence and Consistency
• The Case for Lifetime Reliability-Aware Microprocessors
• The Vector-Thread Architecture
• Wire Delay is not a problem for SMT (in the Near Future)
• Microarchitecture Optimizations for Exploiting Memory-Level Parallelism
• Memory Ordering: A Value-based Approach
• Synchroscalar: A Multiple Clock Domain Power-Aware Tile-Based Embedded
• Prophet-Critic Hybrid Branch Prediction
• Power Awareness Through Selective Dynamically Optimized Traces
• An Overview of the BlueGene/L Supercomputer
• Qos for High-Performance SMT Processorys in Embedded Systems
• Techniques to Reduce the Soft Error Rate of a High Performance Microprocessor
• Exploiting Resonant Behavior to Reduce Inductive Noise
• Evaluating the Imagine Stream Architecture
• Physical Register Inlining

Sign up to present a paper in class.