CSE 590G

FALL 2003

Note room change:  EE1 M406,  Tuesdays 12:30 - 1:20


Schedule:

 

Date

Presenter

Paper

October 10  

Andrew

Universal Mechanisms for Data Parallel Architectures

October 17

Doug

Half-price Architectures

October 24

Sam

Processor Acceleration through Automated Instruction Set Customization

October 31

Charlie & Lillie

Scalable Hardware Memory Disambiguation for High ILP Processors

November 7

Martha and Muthu

Implicitly Multithreaded Architectures

November 14

Andy

A Low-Level Virtual Instruction Set Architecture

November 21

Steve

WaveScalar

December 5

Luke

Comparing Program Phase Detection Techniques

If any changes need to occur to the schedule please send email to sgilmore@cs.washington.edu.