CSE 590G - ARCHITECTURE LUNCH

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Spring, 2001

Tuesdays, 12:30, EE1 042

Professor Susan Eggers & Patrick Crowley

In this quarter's architecture seminar, we will survey the literature on application specific processing.

In particular, we will consider microprocessor architectures specifically tailored for: network communication, media processing, database workloads, and cryptography. (We might also read an FPGA/reconfigurable paper if we can find a good one.) We will wrap up this component of the seminar with a group discussion on open problems and opportunities for further research in this area.

The papers for this quarter are organized below according to the four categories mentioned above. Each week, the class will most likely only need to read one paper; the presenter and other interested parties can look to the other papers/resources listed in each category for background material. If there's interest, of course, we could have two people present a different but related paper each week.

Network Communication

Network Processors 1

On the Performance of Multithreaded Architectures for Network Processors
Crowley, Fiuczynski and Baer (UW TR)

For background info, see: Characterizing Processor Architectures for Programmable Network Interfaces
Crowley, Fiuczynski, Baer, Bershad (ICS 2000)

Network Processors 2

Cache Memory Design for Network Processors
Chiueh & Pradhan (IEEE Micro, 2000)

Media Processing

Media Processing 1

We will take another look at the Imagine project from Stanford. The presentation of this material should include a quick overview of the project, in addition to the new contributions in the latest paper that we'll all be reading.

Efficient Conditional Operations for Data-parallel Architectures
Kapasi, Dally, et al. (MICRO-33)
Imagine overview presentation from HotChips
Imagine overview paper from MICRO-31

Media Processing 2

The MAP-CA is Equator's second generation vliw-based media processor. (Rumor has it that we have a bit of departmental knowledge about what happens at Equator.)

MAP-CA VLIW-based Media Processor
Basoglu, Zhao, Kojima, Kawaguchi

Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing
Barroso et al. (ISCA 2000)
WRL Database Research Group web site:

Cryptography

Crypto 1

We'll look at Todd Austin's ISCA 2001 paper on the Cryptomaniac project.

CryptoManiac: A Fast Flexible Architecture for Secure Communication
Wu, Weaver, Austin (ISCA 2001)

Crypto 2

There's been quite a bit of work done on FPGA-based crypto implementations. We'll take a look at this paper (from Scott Hauck) to see how it compares to Austin's approach.

A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA
Leong, et al. (FCCM 2000)

Miscellaneous Papers

Based on the schedule as it stands now, we'll have one empty slot at the end of the quarter in which to discuss one of the recently published papers listed below. If you're interested in presenting one of these on the last day of class, send me some mail (pcrowley@cs).

We are using a web-based signup tool to pick papers to present in class. If you have problems, please send email to rose@cs.washington.edu and let him know specific details about the problem.

• Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors, Cintra, Martinez, and Torrellas (ISCA 2000)
• HLS: Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs, Oskin, Chong, and Farrens (ISCA 2000)
• What's Ahead for Embedded Software? Lee (Computer, September 2000)
• Recency-based TLB Preloading, Saulsbury, Dahlgren, and Stenstrom (ISCA 2000)
• Memory Access Scheduling, Rixner, Dally, Kapasi, Mattson, and Owens (ISCA 2000)
• On the Value Locality of Store Instructions, Lepak and Lipasti (ISCA 2000)
• Multiple-Banked Register File Architectures, Cruz, Gonzalez, Valero, and Topham (ISCA 2000)
• Morph: Adding an Energy Gear to a High Performance Microarchitecture for Embedded Applications, Kogge and Freeh (Kool Chips Workshop)
• Defect Tolerant Molecular Electronics: Algorithms, Architectures and Atoms, Keukes (MICRO-33)
• Silent Stores for Free, Lepak and Lipasti (MICRO-33)
• On Pipelining Dynamic Instruction Scheduling Logic, Stark, Brown and Patt (MICRO-33)
• Efficient Checker Processor Design, Chatterjee, Weaver and Austin (MICRO-33)
• Two-Level Hierarchical Register File Organization for VLIW Processors, Zalamea, Llosa Ayguade and Valero (MICRO-33)
• PipeRench Implementation of the Instruction Path Coprocessor, Chou, Pillai, Schmit and Shen (MICRO-33)
• A Static Power Model for Architects, Butts and Sohi (MICRO-33)
• Register Integration: A Simple and Efficient Implementation, Roth and Sohi (MICRO-33)
• Slipstream Processors, Purser, Sundaramoorthy and Rotenberg (ASPLOS 2000) and A Study of Slipstream Processors, Purser, Sundaramoorthy and Rotenberg (MICRO-33)
• Relational Profiling": Enabling Thread-Level Parallelism, Heil and Smith (MICRO-33)
• Increasing the Size of Atomic Instruction Blocks Using Control, Patel, Tung, Bose and Crum (MICRO-33)
• Reducing the Wire Delay Penalty through Value Prediction, Parcerisa and Gonzalez (MICRO-33)
• Instruction Distribution Heuristics for Quad-Cluster, Baniasadi and Moshovos (MICRO-33)
• Performance Improvement with Circuit-Level Speculation, Liu and Lu (MICRO-33)
• Predictor-Directed Stream Buffers, Sherwood, Sair and Calder (MICRO-33)
• Hardware Support for Dynamic Activation 0f Compiler-Directed Computation Reuse, Connors, Hunter, Cheng and Hwu (ASPLOS 2000)
• OS and Compiler Considerations in the Design of the IA-64 Architecure, Zahir, Ross, Morris and Hess (ASPLOS 2000)
• Software Profiling for Hot Path Prediction: Less is More, Duesterwald and Bala (ASPLOS 2000)
• Efficient and Flexible Value Sampling, Burrows, Erlingson, Leung, Vandevoorde, Waldspurger, Walker and Weihl (ASPLOS 2000)
• Power Aware Page Allocation, Lebeck, Fan, Zeng and Ellis (ASPLOS 2000)
• System Architecture Directions for Networked Sensors Hill, Szewczyk, Woo, Hollar, Culler and Pister (ASPLOS 2000)
• Using Meta-level Compilation to Check FLASH Protocol Code, Chou, Chelf, Engler and Heinrich (ASPLOS 2000)
• Architecture and Design of AlphaServer GS320, Gharachorloo, Sharma, Steely and Van Doren (ASPLOS 2000)
• Designing Computer Systems with MEMS-based Storage, Schlosser, Griffin, Nagle and Ganger (ASPLOS 2000)
• Cache-Conscious Data Placement, Calder, Krintz, John and Austin (ASPLOS 1998)
• Overlapping Execution with Transfer Using Non-Strict Execution for Mobile Programs, Krintz, Calder, Lee and Zorn (ASPLOS 1998)
• Active Pages: A Computation Model for Intelligent Memory, Oskin, Chong and Sherwood (ASPLOS 1998)
• Itsy: Stretching the Bounds of Mobile Computing, Hamburgen, Wallach, Viredaz, Brakmo, Waldspurger, Bartlett, Mann and Farkas (IEEE Computer, April 2001)
• Toward Quantum Computation: A Five-Qubit Quantum Processor, Steffen, Vandersypen and Chuang (IEEE Micro, March/April 2001)

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