CSE 590G - ARCHITECTURE LUNCH

Professor Eggers
Autumn 2000

We are trying a new signup tool to pick papers to present in class. If you have problems, please send email to "rose@cs" and let him know specific details about the problem.

Here are the papers for this quarter:

An Analysis of Operating System Behavior on a Simultaneous Multithreaded Architecture, Redstone, Eggers and Levy (ASPLOS 2000)
A Scalable Approach to Three-Level Speculation, Steffan, Colohan, Zhai, and Mowry (ISCA 2000)
Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors, Cintra, Martinez, and Torrellas (ISCA 2000)
Transient Fault Detection via Simultaneous Multithreading, Reinhardt and Mukherjee (ISCA 2000)
HLS: Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs, Oskin, Chong, and Farrens (ISCA 2000)
Wattch: A Framework for Architectural-Level Power Analysis and Optimizations, Brooks, Tiwari, and Martonosi (ISCA 2000)
What's Ahead for Embedded Software? Lee (Computer, September 2000)
Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower, Vijayakrishnan, Kandemir, Irwin, Kim, and Ye (ISCA 2000)
A Fully Associative Sofware-Managed Cache Disign, Hallnor and Reinhardt (ISCA 2000)
Recency-based TLB Preloading, Saulsbury, Dahlgren, and Stenstrom (ISCA 2000)
Memory Access Scheduling, Rixner, Dally, Kapasi, Mattson, and Owens (ISCA 2000)
Understanding the Backward Slices of Performance Degrading Instructions, Zilles and Sohi (ISCA 2000)
On the Value Locality of Store Instructions, Lepak and Lipasti (ISCA 2000)
An Analysis in Operating System Behavior on a Simultaneous Multithreaded Architecture, Redstone, Levy, Eggers (ASPLOS 2000)
Performance Analysis of the Alpha 21264-based Compaq ES40 System, Cvetanovic and Kessler (ISCA 2000)
Lx: A Technology Platform for Customizable VLIW Embedded Processing, Faraboschi, Brown, Fisher, Desoli, and Homewood (ISCA 2000)
Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures, Agarwal, Hrishikesh, Keckler, and Burger (ISCA 2000)
Instruction Path Coprocessors, Chou and Shen (ISCA 2000)
Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing, Barroso, Charachorloo, McNamara, Nowatzyk, Qadeer, Sano, Smith, Stets, and Verghese (ISCA 2000)
Multiple-Banked Register File Architectures, Cruz, Gonzalez, Valero, and Topham (ISCA 2000)

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