548 - Winter 2005
Where:
MGH 288
When:
M,W 3 - 4:20
Instructor:
Mark Oskin, oskin@cs.washington.edu
Teaching Assistant:
Andrew Putnam, aputnam@cs.washington.edu
Handouts
Syllabus
Final exam
Schedule
Date
Subject
Presenter
HW/SW Interface Part 1
1/5
RISC
Retrospective on High-Level Language Computer Architecture
A VLSI RISC
Optional:
CryptoManiac: A Fast Flexible Architecture for Secure Communication
Optional: H&P 2.1 - 2.9, 2.10 - 2.16
Anna & Jessica
1/10
VLIW & Vector
A VLIW Archicture and the ELI-512
A VLIW Archicture -- Retrospective
The CRAY-1 Computer System
Optional:
Alpha versus IA-64 (From DEC/Compaq's perspective)
Optional:
Fast Temporary Storage for Serial and Parallel Execution
Optional:
An Analysis of the Cray-1 Computer
Jeff & Xu
1/12
Decoupled
Decoupled Access/Execute Architectures
Retrospective
Kasia & Lillie
OOO Algorithms
1/19
Scoreboarding
Excerpts from Design of a Computer: the Control Data 6600
Parallel Operation in the Control Data 6600
Adrienne
1/24
Tomasulo's Algorithm
An Efficient Algorithm for Exploiting Multiple Arithmetic Units
HPS, a new microarchitecture: rationale and introduction
Jiun-Hung
&
Michelle
1/26
The Microarchitecture of SuperScalar Processors
Scott & Tobias
Widgets
1/31
Branch prediction
(skim)
A Study of Branch Prediction Strategies
Retrospective: A Study of Branch Prediction Strategies
An Analysis of Correlation and Predictability: What Makes Two Level Branch Predictors Work
Optional:
A Language for Describing Predictors for Automatic Synthesis
Optional: H&P Pages 196-215
Ning & Yuhan
1/2
Load/store queue
Reducing Design Complexity of the Load/Store Queue
Kasia
2/7
Caching
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
Improving Direct Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers
Improving Direct Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers - Retrospective
Optional: Section in H&P about caches as background depending upon your prior experience
Midterm practice will be handed out
Jeff & Lillie
2/9
Pentium 4
Pentium4 Microarchitecture
Pentium4 Microarchitecture (Slides)
optional:
IA32 Optimization Guide
optional:
IA32 Optimization Manual
optional:
IA32 Reference Volume 1
optional:
IA32 Reference Volume 2
optional:
IA32 Reference Volume 3
optional:
x86 ISA Reference
optional:
i386 ISA reference (text)
Jiun-Hung & Tobias
2/14
Midterm practice "due"
How to survive the midterm
Midterm handed out
2/16
Putnam: Midterm Q/A
2/18
Midterm due
2/23
Benchmarking and Simulation
Twelve Ways to Fool the Masses
Measuring Experimental Error in Microprocessor Simulation
Errata on Measuring Experimental Error in Microprocessor Simulation
Andrew
2/28
Wires
Clock Rate versus IPC
Optimizing Pipelines for Power and Performance
Anna & Ning
3/2
Limits of Control Flow
Limits of Control Flow on Parallelism
WaveScalar
Final Report Draft Due
Michelle & Yuhan
3/6
Final Report Due at Midnight
3/7
In-Class Presentations
- Anna & Jeff
- Jiun-Hung
- Michelle & Ning
- Adrienne & Xu
3/9
In-Class Presentations
- Scott
- Kasia & Lillie
- Yuhan
- Tobias