CSE 548, Fall 2002

CSE 548 - Fall 2002

Computer Systems Architecture

Instructor

Mark Oskin
oskin@cs.washington.edu
Office: 325C Sieg
Office Hours: TBA

Lecture Tuesday & Thursday 10:30 - 11:50 EE1 003

Administrative support

Mike Kummer
kummer@cs.washington.edu
Office: 323F

Announcements:

Welcome!
Course handout/syllabus (pdf)
548 Email archive

Homeworks

Project (pdf)
Homework (pdf)
Old 378 Final, Due 10/10

Readings and Lecture Notes

Tuesday 10/1	Introduction
Thursday 10/3	Retrospective on High-Level Language Computer Architecture A VLSI RISC H&P 2.1 - 2.9 Optional: H&P 2.10 - 2.16 Optional: CryptoManiac: A Fast Flexible Architecture for Secure Communication"
Tuesday 10/8	Canceled -- ASPLOS
Thursday 10/10	The Engineering Design of the Strech Computer H&P Appendix A.1 - A.4
Tuesday 10/15	Excerpts from Design of a Computer: the Control Data 6600 H&P 3.1, A.8 - A.11 Optional: Parallel Operation in the Control Data 6600, 1964
Thursday 10/17	An Efficient Algorithm for Exploiting Multiple Arithmetic Units H&P 3.2 & 3.3
Tuesday 10/22	Canceled -- Univeristy "stuff" (to put it kindly)
Thursday 10/24	A VLIW Archicture and the ELI-512 Alpha versus IA-64 (From DEC/Compaq's perspective) A VLIW Archicture -- Retrospective
Tuesday 10/29	H&P 3.4 A Study of Branch Prediction Strategies Retrospective: A Study of Branch Prediction Strategies A Language for Describing Predictors for Automatic Synthesis Optional: An Analysis of Correlation and Predictability: What Makes Two Level Branch Predictors Work
Thursday 10/31	H&P 5.1 - 5.7 Lockup Free Instruction Fetch/Prefetch Cache Organization Lockup Free Instruction Fetch/Prefetch Cache Organization - Retrospective Improving Direct Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers Improving Direct Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers - Retrospective
Tuesday 11/5	MIDTERM
Thursday 2/7	Clock Rate Versus IPC: The End of the Road for Conventional Microarchitectures
Tuesday 2/12	SMT Maximizing On Chip Parallelism SMT Maximizing On Chip Parallelism - Retrospective The Case for a Single Chip Multiprocessor H&P Section 6.9, 6.10 & 6.16
Thursday 2/14	A Preliminary Architecture for a Basic Dataflow Processor WaveScalar - This paper is a draft, please do not distribute
Tuesday 10/19	ZebraNet Quantifying the Energy Consumption of a Pocket Computer
Thursday 12/5	Pentuim 4 Alpha 21264a Skim: UltraSparc III Skim: Power 4
Monday 12/9	Nanofabrics: Spatial Computing using Molecular Electronics A Practical Architecture for Reliable Quantum Computers A New Algebraic Foundation for Quantum Programming LanguagesThis paper is not yet published, please do not redistribute it.