C51 COMPILER V6.00 FPGA 05/29/2001 18:52:39 PAGE 1 C51 COMPILER 6.00, COMPILATION OF MODULE FPGA OBJECT MODULE PLACED IN .\fpga.OBJ COMPILER INVOKED BY: d:\app\keil\eval\C51\BIN\C51.EXE .\fpga.c BROWSE OBJECTEXTEND DEBUG stmt level source 1 /* fpga.c */ 2 3 #include "door.h" 4 #include "fpga.h" 5 6 /* # of 25 ms before timeout */ 7 /* time out flag */ 8 static bit done = 0; 9 static bit timeOut = 0; 10 static bit runFPGA = 1; 11 12 unsigned char subseconds = 0; 13 unsigned char seconds = 0; 14 15 char xdata *led = 0x0f000; // the FPGA is configured to memory map led to this address 16 17 void FPGA_Task() { 18 1 /* set timer */ 19 1 PCON = PCON | 0x80; 20 1 TMOD = 0x21; 21 1 22 1 /* Set up and enable Timer0 for a 1 millisecond timer */ 23 1 TL0 = FPGA_RELOAD_LO_B; /* Load the timer high and low bytes */ 24 1 TH0 = FPGA_RELOAD_HI_B; 25 1 EA = 1; /* Enable the global interrupt */ 26 1 EX1 = 1; /* Enable the external interrupt 1 */ 27 1 IT0 = 1; /* Enable the TCON for falling edge trigger */ 28 1 29 1 runFPGA = 1; 30 1 done = 0; 31 1 timeOut = 0; 32 1 // T0 = 1; // Request = 1 33 1 T1 = 1; // p3.5: pin 22, inv(Request) = 1 34 1 TR0 = 1; /* Start the timer 0 */ 35 1 ET0 = 1; /* Enable the timer interrupt 0 (Page 55) */ 36 1 PT0 = 1; /* Timer 0 Interrupt Priority */ 37 1 IE0 = 0; 38 1 *led = 0x52; // 7 39 1 while (runFPGA) { 40 2 if((done) || (timeOut)) 41 2 { 42 3 *led = 0xFF; //8 43 3 ET0 = 0; // disable timer interrupt 0 44 3 EX0 = 0; // disable ext int 0 45 3 EX1 = 0; // disable ext int 1 46 3 EA = 0; 47 3 T1 = 0; // p3.5: pin 22, inv(Request) = 0 48 3 if(timeOut) 49 3 { 50 4 *led = 0x7B; //9 51 4 // reset FPGA; 52 4 } 53 3 state = DETECTING_USER; 54 3 runFPGA = 0; 55 3 //return; C51 COMPILER V6.00 FPGA 05/29/2001 18:52:39 PAGE 2 56 3 } 57 2 } 58 1 }/* end FPGA_Task */ 59 void FPGA_Timer0_Handler() { 60 1 TL0 = TL0 + FPGA_RELOAD_LO_B ; // Load the timer high and low bytes 61 1 TH0 = FPGA_RELOAD_HI_B; 62 1 subseconds = subseconds + 1; 63 1 64 1 if (subseconds == 100) { // and check for one/tenth-second rollover 65 2 subseconds = 0; 66 2 seconds = seconds + 1; 67 2 if(seconds == 4) 68 2 { 69 3 timeOut = 1; 70 3 seconds = 0; 71 3 } 72 2 } 73 1 } /* end of FPGA_Timer0_Handler() */ 74 75 void FPGA_Ext1_Handler() { 76 1 //*led = 0x5D; //2 77 1 done = 1; 78 1 IE0 = 0; 79 1 } /* end of FPGA_Ext1_Handler() */ 80 81 /* 82 case 0: value = 0x77; init =1; break; 83 case 1: value = 0x12; break; 84 case 2: value = 0x5D; break; 85 case 3: value = 0x5B; break; 86 case 4: value = 0x3A; break; 87 case 5: value = 0x6B; break; 88 case 6: value = 0x6F; break; 89 case 7: value = 0x52; break; 90 case 8: value = 0xFF; break; 91 default: value = 0x7B; 92 */ 93 94 95 96 97 98 99 100 MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 122 ---- CONSTANT SIZE = ---- ---- XDATA SIZE = ---- ---- PDATA SIZE = ---- ---- DATA SIZE = 4 ---- IDATA SIZE = ---- ---- BIT SIZE = 3 ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)