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|
| VGA Interface Test Script
|
| Frans Faizal (9810315)
| Jimmy Muliawan (9811074)
|
| Design Problem #9
| CSE 467 AB
|
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| The file has been automatically generated by
| the Script Editor File Wizard version 2.0.1.89
| 
| Copyright © 1998 Aldec, Inc.
 
 
| Initial settings
delete_signals
set_mode functional
restart 
stepsize 10 ns	| 20ns clock
clock CLK 0 1
 
| Vector Definitions

vector DataIn DataIn[7:0] 
vector pixel pixel[5:0] 
vector Address Address[14:0]
radix decimal DataIn pixel 
radix hex Address 

| Watched Signals and Vectors

watch CLK Read DataIn pixel  
watch HSYNC VSYNC

| Perform Simulation

assign DataIn 20\D

cycle 70