/* fpga.h */

/* reload value for 16-bit 25 ms counter assuming 22MHz clock */
#define RELOAD      5208        /* Reload value for 5 milliseconds for 25MHz */
#define FPGA_RELOAD_HI_B   ((-RELOAD)&(0xFF))      /* Calculate low and high bytes */
#define FPGA_RELOAD_LO_B   (((-RELOAD)&(0xFF00))/(256))

void FPGA_Task();

/* called by Timer0 ISR in CHECKING_ID state */
void FPGA_Timer0_Handler();
	
/* called by Ext1 ISR in CHECKING_ID state */
void FPGA_Ext1_Handler();


/* BUSY signal from the FPGA */
//sbit Busy = P3^3;

/* REQ signal to the FPGA */
//sbit Request = P3^5;