C51 COMPILER V6.00 FPGA                                                                    05/29/2001 14:32:58 PAGE 1   


C51 COMPILER 6.00, COMPILATION OF MODULE FPGA
OBJECT MODULE PLACED IN .\fpga.OBJ
COMPILER INVOKED BY: d:\app\keil\eval\C51\BIN\C51.EXE .\fpga.c OBJECTEXTEND DEBUG

stmt level    source

   1          /* fpga.c */
   2          
   3          #include "fpga.h"
   4          #include "W77C32.H"
   5          
   6          /* # of 25 ms before timeout */
   7          /* time out flag */
   8          static bit timeOut = 0;
   9          static bit done = 0;
  10          static bit run = 1;
  11          unsigned char subseconds = 0;
  12          unsigned char seconds = 0;
  13          unsigned char loop = 0;
  14          
  15          char xdata *led = 0x0f000;  // the FPGA is configured to memory map led to this address
  16          
  17          void main()
  18          {
  19   1      //	*led = 0x07;
  20   1      	while(loop < 3)
  21   1      	{
  22   2      //		*led = 0x12;		// 1
  23   2      		FPGA_Task();
  24   2      		loop = loop + 1;
  25   2      //		*led = 0x77;		// 0
  26   2      //		*led = loop;
  27   2      	}
  28   1      	while(1){}
  29   1      }
  30          void FPGA_Task() {
  31   1      
  32   1      	/* set timer */
  33   1      	PCON = PCON | 0x80;
  34   1      	TMOD = 0x21;
  35   1      //	TH1 = 249;
  36   1      //	TR1 = 1;
  37   1      
  38   1      	/* Set up and enable Timer0 for a 1 millisecond timer   */
  39   1      	TL0 = FPGA_RELOAD_LO_B;	/* Load the timer high and low bytes        */
  40   1      	TH0 = FPGA_RELOAD_HI_B;
  41   1      	EA = 1;				/* Enable the global interrupt  */
  42   1      //	EX0 = 1;			/* Enable the external interrupt 0 */
  43   1      	EX1 = 1;			/* Enable the external interrupt 1 */
  44   1      	IT0 = 1;			/* Enable the TCON for falling edge trigger */
  45   1      
  46   1      	run = 1;
  47   1      	done = 0;
  48   1      	timeOut = 0;
  49   1      	T1 = 0; 			// p3.5: pin 22, inv(Request) = 1
  50   1      	TR0 = 1;			/* Start the timer 0             */
  51   1      	ET0 = 1;			/* Enable the timer interrupt 0 (Page 55) */
  52   1      	PT0 = 1;			/* Timer 0 Interrupt Priority */
  53   1      //	IE0 = 0;
  54   1      	*led = 0x3A;	// 4
  55   1      	while (run) {
C51 COMPILER V6.00 FPGA                                                                    05/29/2001 14:32:58 PAGE 2   

  56   2      		if((done) || (timeOut))
  57   2      	 	{
  58   3      			*led = 0xFF; //8
  59   3      			run = 0;
  60   3      			ET0 = 0;			// disable timer interrupt 0
  61   3      			EX0 = 0;			// disable ext int 0
  62   3      			EX1 = 0;			// disable ext int 1
  63   3      			EA = 0;
  64   3      			T1 = 1;				// p3.5: pin 22, inv(Request) = 0
  65   3      			if(timeOut) 
  66   3      			{
  67   4      				*led = 0x7B;	//9
  68   4      				// reset FPGA;
  69   4      			}
  70   3      //			state = DETECTING_USER;
  71   3      		}
  72   2      	}
  73   1      }/* end FPGA_Task */
  74          
  75          //void FPGA_Ext1_Handler() interrupt 0 {
  76          void FPGA_Ext1_Handler() interrupt 2 {
  77   1      //*led = 0x5D;	//2
  78   1      	done = 1;
  79   1      	IE0 = 0;
  80   1      } /* end of FPGA_Ext1_Handler() */
  81          
  82          
  83          void FPGA_Timer0_Handler() interrupt 1 {
  84   1      	TL0 = TL0 + FPGA_RELOAD_LO_B ;   // Load the timer high and low bytes        
  85   1      	TH0 = FPGA_RELOAD_HI_B;
  86   1      	subseconds = subseconds + 1;
  87   1      
  88   1      	if (subseconds == 100) {      // and check for one/tenth-second rollover        
  89   2          	subseconds = 0;
  90   2          	seconds = seconds + 1;
  91   2      		if(seconds == 4)
  92   2      		{
  93   3      			timeOut = 1;
  94   3      			seconds = 0;
  95   3      		}
  96   2       	}	
  97   1      } /* end of FPGA_Timer0_Handler() */
  98          
  99          
 100          /*	
 101          	case 0:		value = 0x77; init =1;		break;
 102          	case 1:		value = 0x12;		break;
 103          	case 2:		value = 0x5D;		break;
 104          	case 3:		value = 0x5B;		break;
 105          	case 4:		value = 0x3A;		break;
 106          	case 5:		value = 0x6B;		break;
 107          	case 6:		value = 0x6F;		break;
 108          	case 7:		value = 0x52;		break;
 109          	case 8:		value = 0xFF; 		break;
 110          	default:		value = 0x7B;
 111          */
 112          
 113          
 114          


MODULE INFORMATION:   STATIC OVERLAYABLE
C51 COMPILER V6.00 FPGA                                                                    05/29/2001 14:32:58 PAGE 3   

   CODE SIZE        =    141    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =      5    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =      3    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)