|===============SETUP===============
|-----Simulator Settings-----
delete_signals    | delete any existing waveforms in the window
clpr sim_out.out  | clear the output file
restart           | restart to time zero
set_mode functional

|-----Vectors-----
| Assign names to groups of related signals here.  Also, you can specify
| the radix/base in which to display these signals.

vector BUS H5/PADXDATA[3:0]
vector READDATA DATA[7:0]
vector WRITEDATA WRITEDATAB[7:0]
vector ADDRB ADDRB[16:0]
vector ADDRA MEMY[7:0] MEMX[8:0]
vector PADCOM H5/PADCOM[1:0]
vector VCNT VCNT[9:0]
vector HCNT HCNT[9:0]
vector PADADDR	H4/PADADDR[16:0]
vector PADDATA	H4/PADDATA[7:0]

vector PADSTROBE H5/PADSTROBE

|-----Watch Statements-----
| List any signals you want to see in the waveform viewer, or which you
| want to output to a file.

watch CLK H5/NEWCMD WRITEB 
watch BUSYB H5/PADXBUSY H5/ENREADDATA
watch H4/PADWR H4/PADOE
|watch PADDATA[3:0]
|watch PADDATA[0]
watch H3/PADHSYNC H3/PADVSYNC
watch H3/PADRGB[5:0]
watch PC_D0

|-----Clock Settings----- 
| Setup various clock signals.  Also, can specify their shape and timing.
stepsize 10ns   | This gives a clock period of 20ns
clock CLK 0 1

|===============SIMULATION===============
|
| The following commands will be useful:
|   'assign' - to assign values to pins/wires (use 'release' to stop
|                driving a signal)
| We'll send the Manchester data every 64 ns (about 3 clocks)
| (Change this to between 60 and 70 ns and it still works)

assign PADSTROBE 0
assign PADCOM 00\B
|assign BUSY 0
assign BUS 0\H
assign READDATA 00\H
assign PC_D0 1
sim 20ns
assign PC_D0 0
sim 20ns
assign PADCOM 01\B		| ADDR
assign BUS F\H		| Nibble 0 of CDEF address
sim 60ns
assign PADSTROBE 1
sim 60ns
assign BUS E\H		| Nibble 1 of address
sim 60ns
assign PADSTROBE 0
sim 60ns
assign BUS D\H		| Nibble 2 of address
sim 60ns
assign PADSTROBE 1
sim 60ns
assign BUS C\H		| Nibble 3 of address
sim 60ns
assign PADSTROBE 0
sim 60ns
assign PADCOM 10\B		| WRITE
assign BUS 1\H		| Low nibble of 21
sim 60ns
assign PADSTROBE 1
sim 60ns
assign BUS 2\H		| High nibble
sim 60ns
assign PADSTROBE 0

sim 700ms			| Wait for busy to fall low

|assign BUSY 1		| Write port is busy
sim 80ns
|assign Busy 0
sim 60ns
assign BUS 3\H		| Next write: low nibble of 43
sim 60ns
assign PADSTROBE 1
sim 60ns
assign BUS 4\H		| High nibble
sim 60ns
assign PADSTROBE 0
sim 60ns
assign BUS 5\H		| Next write: low nibble of 65
sim 60ns
assign PADSTROBE 1
sim 60ns
assign BUS 6\H		| High nibble
sim 60ns
assign PADSTROBE 0
sim 60ns
assign PADCOM 01\B		| Start a new ADDR
assign BUS 7\H		| Nibble 0 of 4567 address
sim 60ns
assign PADSTROBE 1
sim 60ns
assign BUS 6\H		| Nibble 1 of address
sim 60ns
assign PADSTROBE 0
sim 60ns
assign BUS 5\H		| Nibble 2 of address
sim 60ns
assign PADSTROBE 1
sim 60ns
assign BUS 4\H		| Nibble 3 of address
sim 60ns
assign PADSTROBE 0
sim 60ns
assign PADCOM 11\B		| READ
release BUS     	| Tristate pad signals.  For some reason, this doesn't work
sim 60ns
assign PADSTROBE 1
|assign BUSY 1		| Read port busy
sim 80ns
|assign BUSY 0
sim 20ns
assign READDATA CD\H  | Read value - low nibble transfered
sim 60ns
assign PADSTROBE 0	| transfer high nibble
sim 60ns
assign PADSTROBE 1  | Read next address
assign READDATA A9\H  | Next read value - low nibble
sim 60ns
assign PADSTROBE 0  | high nibble
sim 100ns
sim 40ns
sim 40ns

quit