CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: Warning L-1/C0 : #0 Warning: The net '/MemControl/ReadA' is a feed through net. (FE-CHECK-9) CM: 0 error(s) 1 warning(s) found CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: CM: Synthesizing... CM: Error L57/C0 : #0 Error: Undefined variable 'Busy' used near symbol ")" on line 57 in file BusControl.v (VE-3) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L69/C0 : #0 Error: Undefined variable 'HOLDREAD1' used near symbol ":" on line 69 in file BusControl.v (VE-3) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L81/C0 : #0 Error: Undefined variable 'INC' used near symbol "=" on line 81 in file BusControl.v (VE-3) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L176/C0 : #0 Error: syntax error at or near token 'end' (File: J:/cse477/Spring1999/Xbus/XBUSVGA/BusControl.v Line: 176) (VE-0) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'ADDRDATAREGS' successfully updated CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'BUSCONTROL' successfully updated CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'ADDRDATAREGS' successfully updated CM: 0 error(s) 0 warning(s) found CM: Warning L-1/C0 : #0 Warning: The net '/MemControl/ReadA' is a feed through net. (FE-CHECK-9) CM: 0 error(s) 1 warning(s) found CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'READDATAREG' successfully updated CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'BUSCONTROL' successfully updated CM: CM: Synthesizing... CM: Error L33/C0 : #0 Error: Undefined variable 'Addr' used near symbol "[" on line 33 in file BusControl.v (VE-3) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'BUSCONTROL' successfully updated CM: CM: Synthesizing... CM: Error L53/C0 : #0 Error: Continuous Assignment made to reg 'read' near symbol "=" on line 53 in file pan.v. (VE-17) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L52/C0 : #0 Error: Continuous Assignment made to reg 'read' near symbol "=" on line 52 in file pan.v. (VE-17) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'PAN' successfully updated CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'PAN' successfully updated CM: CM: Synthesizing... CM: Error L60/C0 : #0 Error: Undefined variable 'pan' used near symbol ")" on line 60 in file pan.v (VE-3) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'PAN' successfully updated CM: CM: Synthesizing... CM: Error L-1/C0 : #0 Error: Port 'MemBusy' not defined in module terminal list but defined in an input/output/inout statement in file BusControl.v (VE-13) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L-1/C0 : #0 Error: Port 'ReadMem' not defined in module terminal list but defined in an input/output/inout statement in file BusControl.v (VE-13) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L140/C0 : #0 Error: Undefined variable 'Addr0' used near symbol "&&" on line 140 in file BusControl.v (VE-3) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L165/C0 : #0 Error: syntax error at or near token 'MemBusy' (File: C:/cse467/projects/xbusvga/BusControl.v Line: 165) (VE-0) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'BUSCONTROL' successfully updated CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'ADDRDATAREGS' successfully updated CM: CM: Synthesizing... CM: Warning L-1/C0 : #0 Warning: The net '/MemControl/ReadA' is a feed through net. (FPGA-CHECK-9) CM: 0 error(s) 1 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Operation failed CM: CM: Synthesizing... CM: Warning L-1/C0 : #0 Warning: The net '/MemControl/ReadA' is a feed through net. (FPGA-CHECK-9) CM: 0 error(s) 1 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'MEMCONTROL' successfully updated CM: CM: Synthesizing... CM: Warning L-1/C0 : #0 Warning: The net '/MemControl/ReadA' is a feed through net. (FPGA-CHECK-9) CM: 0 error(s) 1 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'MEMCONTROL' successfully updated CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'BUSCONTROL' successfully updated CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'READDATAREG' successfully updated CM: 0 error(s) 0 warning(s) found CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'BUSCONTROL' successfully updated CM: 0 error(s) 0 warning(s) found CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'ADDRDATAREGS' successfully updated CM: 0 error(s) 0 warning(s) found CM: CM: Synthesizing... CM: Error L-1/C0 : #0 Error: Port 'LaserPoint' not defined in module terminal list but defined in an input/output/inout statement in file SendData.v (VE-13) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L-1/C0 : #0 Error: Port 'Bank' not defined in module terminal list but defined in an input/output/inout statement in file SendData.v (VE-13) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L29/C0 : #0 Error: Undefined variable 'sendInfo' used near symbol "=" on line 29 in file SendData.v (VE-3) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L43/C0 : #0 Error: Undefined variable 'sendInterrupt' used near symbol "=" on line 43 in file SendData.v (VE-3) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L43/C0 : #0 Error: Illegal assignment to wire 'InterruptSignal' near symbol "=" on line 43 in file SendData.v. (VE-7) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Warning L-1/C0 : #0 Warning: Variable 'setInterruptHigh' is driven in more than one process or block in file D:/bek/Cam/VGACAM/SendData.v This may cause mismatch between simulation and synthesis. (HDL-220) CM: Error L-1/C0 : #0 Error: The net '/SendData/setInterruptHigh' has more than one driver. (FPGA-CHECK-5) CM: 1 error(s) 1 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Warning L-1/C0 : #0 Warning: Variable 'setInterruptHigh' is driven in more than one process or block in file D:/bek/Cam/VGACAM/SendData.v This may cause mismatch between simulation and synthesis. (HDL-220) CM: Error L-1/C0 : #0 Error: The net '/SendData/setInterruptHigh' has more than one driver. (FPGA-CHECK-5) CM: 1 error(s) 1 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Operation failed CM: 0 error(s) 0 warning(s) found CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Operation failed CM: CM: Synthesizing... CM: Error L42/C0 : #0 Error: syntax error at or near token '' (File: D:/bek/Cam/VGACAM/SendData.v Line: 42) (VE-0) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Operation failed CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Operation failed CM: CM: Synthesizing... CM: Error L27/C0 : #0 Error: Continuous Assignment made to reg 'PreviousBank' near symbol "<=" on line 27 in file SendInfo.v. (VE-17) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L38/C0 : #0 Error: Illegal assignment to wire 'Rst' near symbol "=" on line 38 in file SendInfo.v. (VE-7) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L38/C0 : #0 Error: Illegal assignment to wire 'Rst' near symbol "=" on line 38 in file SendInfo.v. (VE-7) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L38/C0 : #0 Error: Illegal assignment to wire 'Rst' near symbol "=" on line 38 in file SendInfo.v. (VE-7) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Operation failed CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Operation failed CM: CM: Synthesizing... CM: Error L138/C0 : #0 Error: Illegal assignment to wire 'DataOut' near symbol "=" on line 138 in file SendInfo.v. (VE-7) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Warning L76/C0 : #0 Warning: Variable 'LaserPoint' is being read in routine SendInfo line 76 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L76/C0 : #0 Warning: Variable 'Bank' is being read in routine SendInfo line 76 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L76/C0 : #0 Warning: Variable 'XbusState' is being read in routine SendInfo line 76 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L-1/C0 : #0 Warning: Latch inferred in design 'SendInfo' read with 'hdlin_check_no_latch'. (HDL-307) CM: 0 error(s) 4 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L110/C0 : #0 Error: Illegal assignment to wire 'signalMicroController' near symbol "=" on line 110 in file SendInfo.v. (VE-7) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L110/C0 : #0 Error: Illegal assignment to wire 'signalMicroController' near symbol "=" on line 110 in file SendInfo.v. (VE-7) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Error L112/C0 : #0 Error: syntax error at or near token 'else' (File: D:/bek/Cam/VGACAM/SendInfo.v Line: 112) (VE-0) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Warning L76/C0 : #0 Warning: Variable 'Bank' is being read in routine SendInfo line 76 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L76/C0 : #0 Warning: Variable 'LaserPoint' is being read in routine SendInfo line 76 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L76/C0 : #0 Warning: Variable 'XbusState' is being read in routine SendInfo line 76 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L-1/C0 : #0 Warning: Latch inferred in design 'SendInfo' read with 'hdlin_check_no_latch'. (HDL-307) CM: 0 error(s) 4 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Warning L76/C0 : #0 Warning: Variable 'XbusState' is being read in routine SendInfo line 76 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L-1/C0 : #0 Warning: Latch inferred in design 'SendInfo' read with 'hdlin_check_no_latch'. (HDL-307) CM: 0 error(s) 2 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'SENDINFO' successfully updated CM: CM: Synthesis Successful CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Warning L82/C0 : #0 Warning: Variable 'XbusState' is being read in routine SendInfo line 82 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L82/C0 : #0 Warning: Variable 'WakeUpSignal' is being read in routine SendInfo line 82 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L-1/C0 : #0 Warning: Latch inferred in design 'SendInfo' read with 'hdlin_check_no_latch'. (HDL-307) CM: 0 error(s) 3 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'SENDINFO' successfully updated CM: CM: Warning L82/C0 : #0 Warning: Variable 'XbusState' is being read in routine SendInfo line 82 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L82/C0 : #0 Warning: Variable 'WakeUpSignal' is being read in routine SendInfo line 82 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L-1/C0 : #0 Warning: Latch inferred in design 'SendInfo' read with 'hdlin_check_no_latch'. (HDL-307) CM: 0 error(s) 3 warning(s) found CM: Synthesis successful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Warning L82/C0 : #0 Warning: Variable 'XbusState' is being read in routine SendInfo line 82 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L82/C0 : #0 Warning: Variable 'WakeUpSignal' is being read in routine SendInfo line 82 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L-1/C0 : #0 Warning: Latch inferred in design 'SendInfo' read with 'hdlin_check_no_latch'. (HDL-307) CM: 0 error(s) 3 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'SENDINFO' successfully updated CM: CM: Synthesizing... CM: Warning L82/C0 : #0 Warning: Variable 'XbusState' is being read in routine SendInfo line 82 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L82/C0 : #0 Warning: Variable 'WakeUpSignal' is being read in routine SendInfo line 82 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L-1/C0 : #0 Warning: Latch inferred in design 'SendInfo' read with 'hdlin_check_no_latch'. (HDL-307) CM: 0 error(s) 3 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Warning L82/C0 : #0 Warning: Variable 'XbusState' is being read in routine SendInfo line 82 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L82/C0 : #0 Warning: Variable 'WakeUpSignal' is being read in routine SendInfo line 82 in file 'D:/bek/Cam/VGACAM/SendInfo.v', but does not occur in the timing control of the block which begins there. (HDL-180) CM: Warning L-1/C0 : #0 Warning: Latch inferred in design 'SendInfo' read with 'hdlin_check_no_latch'. (HDL-307) CM: 0 error(s) 3 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'SENDINFO' successfully updated CM: CM: Synthesizing... CM: Error L53/C0 : #0 Error: Illegal assignment to wire 'Send' near symbol "=" on line 53 in file SendData.v. (VE-7) CM: 1 error(s) 0 warning(s) found CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<1>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<3>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<4>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<7>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<0>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<2>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<0>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<6>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<5>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<6>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<4>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<1>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<2>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<7>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<5>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<3>' is a feed through net. (FPGA-CHECK-9) CM: 0 error(s) 16 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'SENDDATA' successfully updated CM: CM: Synthesizing... CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<6>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<2>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<0>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<2>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<4>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<4>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<3>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<5>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<5>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<1>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<6>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<0>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<3>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<7>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<1>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<7>' is a feed through net. (FPGA-CHECK-9) CM: 0 error(s) 16 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Synthesizing... CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<7>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<0>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<6>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<2>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<1>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<2>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<5>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<4>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<3>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<7>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<6>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<4>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<5>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<1>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<3>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<0>' is a feed through net. (FPGA-CHECK-9) CM: 0 error(s) 16 warning(s) found CM: Synthesis succesful (Warnings found) CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'SENDDATA' successfully updated CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<7>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<0>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<6>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<2>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<1>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<2>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<5>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<4>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<3>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<7>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<6>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<4>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<5>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightRow<1>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<3>' is a feed through net. (FPGA-CHECK-9) CM: Warning L-1/C0 : #0 Warning: The net '/SendInfo/BrightCol<0>' is a feed through net. (FPGA-CHECK-9) CM: 0 error(s) 16 warning(s) found CM: 0 error(s) 0 warning(s) found CM: CM: Synthesizing... CM: CM: Use Synthesis/View Report for detailed synthesis report CM: CM: Netlist is up-to-date CM: Symbol 'BLANKPIXEL' successfully updated CM: 0 error(s) 0 warning(s) found CM: 0 error(s) 0 warning(s) found