Loading device database for application ngdanno from file "xbusvga.ncd".
   "xbusvga" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3
Loading device for application ngdanno from file '4010xl.nph' in environment
D:/Xilinx/fndtn.
Reading .ngm file "map.ngm"...
Building NGA image...
Annotating NGA image...
Distributing delays...
WARNING:Anno:26 - NGDANNO found physical components for which 100 percent
   back-annotation is not possible.  (These components are listed below.)  Some
   reasons these components may not be fully back-annotatable include:
   

1. The logic was replicated during physical mapping.
   

2. MAP was directed to optimize the logic through use of the -oe or -os
   option, or the OPTIMIZE or OPT_EFFORT design attribute.
   

3. The component's configuration implies a more complex delay model than can
   be accurately represented in the original design logic.  An example of such a
   configuration is an XC4000-family CLB containing both carry logic and
   multiple flip-flops.
   

Simulation models for the following components will be constructed from the
   NCD netlist.  Signal names buried within these components will be lost.
   H3/L4/MO0_0
   H3/L4/MO0_1
   H3/L4/MO0_2
   H3/L4/MO0_3
   H3/L4/MO0_4
   H3/L4/MO0_5
   H3/L4/MO1_0
   H3/L4/MO1_1
   H3/L4/MO1_2
   H3/L4/MO1_3
   H3/L4/MO1_4
   H3/L4/MO1_5
   HCNT<2>
   HCNT<4>
   HCNT<6>
   U5/C431_N26
   U5/C432_N26
   U5/C758_CINt
   U5/C760_CINt
   U5/N1398
   U5/N1402
   U5/N1404
   U5/N1439
   U5/N1443
   U5/N1445
   U5/N1447
   U5/xstart<1>
   U5/xstart<3>
   U5/xstart<5>
   U5/ystart<1>
   U5/ystart<3>
   VCNT<2>
   VCNT<4>
   VCNT<6>
   XADDRESS<11>
   XADDRESS<13>
   XADDRESS<1>
   XADDRESS<3>
   XADDRESS<5>
   XADDRESS<7>
   XADDRESS<9>
Writing .nga file "xbusvga.nga"...
   150 logical models annotated
   41 physical models annotated