ngdbuild -p xc4010xl-3-pc84 -uc xbusvga.ucf -dd .. C:\XBUS\XBUSVGA\xbusvga.EDN xbusvga.ngd ngdbuild: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc4010xl-3-pc84 -uc xbusvga.ucf -dd .. C:\XBUS\XBUSVGA\xbusvga.EDN xbusvga.ngd Launcher: Executing edif2ngd "C:\XBUS\XBUSVGA\xbusvga.EDN" "c:\xbus\xbusvga\xproj\ver1\xbusvga.ngo" edif2ngd: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Writing the design to "c:/xbus/xbusvga/xproj/ver1/xbusvga.ngo"... Reading NGO file "c:/xbus/xbusvga/xproj/ver1/xbusvga.ngo" ... Reading component libraries for design expansion... Running LogiBLOX expansion on symbol "L1"... Running LogiBLOX expansion on symbol "L2"... Running LogiBLOX expansion on symbol "L4"... Running LogiBLOX expansion on symbol "L5"... Running LogiBLOX expansion on symbol "L6"... Launcher: "SYNCGEN.ngo" is up to date. Loading design module "c:\xbus\xbusvga\xproj\ver1\SYNCGEN.ngo"... Launcher: "BLANKPIXEL.ngo" is up to date. Loading design module "c:\xbus\xbusvga\xproj\ver1\BLANKPIXEL.ngo"... Running LogiBLOX expansion on symbol "L1"... Running LogiBLOX expansion on symbol "L2"... Running LogiBLOX expansion on symbol "L3"... Running LogiBLOX expansion on symbol "L4"... Running LogiBLOX expansion on symbol "L6"... Launcher: "MEMCONTROL.ngo" is up to date. Loading design module "c:\xbus\xbusvga\xproj\ver1\MEMCONTROL.ngo"... Running LogiBLOX expansion on symbol "L1"... Running LogiBLOX expansion on symbol "L16"... Launcher: "BUSCONTROL.ngo" is up to date. Loading design module "c:\xbus\xbusvga\xproj\ver1\BUSCONTROL.ngo"... Launcher: "ADDRDATAREGS.ngo" is up to date. Loading design module "c:\xbus\xbusvga\xproj\ver1\ADDRDATAREGS.ngo"... Launcher: "READDATAREG.ngo" is up to date. Loading design module "c:\xbus\xbusvga\xproj\ver1\READDATAREG.ngo"... Launcher: "PAN.ngo" is up to date. Loading design module "c:\xbus\xbusvga\xproj\ver1\PAN.ngo"... Annotating constraints to design from file "xbusvga.ucf" ... Checking timing specifications ... Checking expanded design ... WARNING:NgdHelpers:334 - logical net "$I133/Q<0>" has no load WARNING:NgdHelpers:334 - logical net "$I133/Q<1>" has no load WARNING:NgdHelpers:334 - logical net "$I133/Q<2>" has no load WARNING:NgdHelpers:334 - logical net "$I133/Q<3>" has no load WARNING:NgdHelpers:334 - logical net "$I133/Q<4>" has no load WARNING:NgdHelpers:334 - logical net "$I133/Q<5>" has no load WARNING:NgdHelpers:334 - logical net "$I133/Q<6>" has no load WARNING:NgdHelpers:334 - logical net "$I133/Q<7>" has no load WARNING:NgdHelpers:357 - clock net "H4/$Net00002_" has non-clock connections WARNING:NgdHelpers:357 - clock net "CLK" has non-clock connections WARNING:NgdHelpers:334 - logical net "PC_D3" has no load WARNING:NgdHelpers:334 - logical net "PC_D5" has no load WARNING:NgdHelpers:334 - logical net "PC_D1" has no load WARNING:NgdHelpers:334 - logical net "PC_D2" has no load WARNING:NgdHelpers:334 - logical net "PC_D7" has no load WARNING:NgdHelpers:334 - logical net "PC_D6" has no load WARNING:NgdHelpers:332 - logical net "PC_S7" has no driver WARNING:NgdHelpers:332 - logical net "PC_S5" has no driver WARNING:NgdHelpers:334 - logical net "PC_D4" has no load WARNING:NgdHelpers:332 - logical net "LED0" has no driver WARNING:NgdHelpers:332 - logical net "LED1" has no driver WARNING:NgdHelpers:332 - logical net "LED2" has no driver WARNING:NgdHelpers:332 - logical net "LED3" has no driver WARNING:NgdHelpers:332 - logical net "LED4" has no driver WARNING:NgdHelpers:332 - logical net "LED5" has no driver WARNING:NgdHelpers:332 - logical net "LED6" has no driver NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 26 Writing NGD file "xbusvga.ngd" ... Writing NGDBUILD log file "xbusvga.bld"... NGDBUILD done. ================================================== map -p xc4010xl-3-pc84 -o map.ncd xbusvga.ngd xbusvga.pcf map: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Reading NGD file "xbusvga.ngd"... Using target part "4010xlpc84-3". MAP xc4000xl directives: Partname = "xc4010xl-3-pc84". Covermode = "area". Pack Unrelated Logic into CLBs targeting 100% of CLB resources. Processing logical timing constraints... Verifying F/HMAP validity based on pre-trimmed logic... Removing unused logic... Packing logic in CLBs... Running cover... Undirected packing... Running physical design DRC... Design Summary: Number of errors: 0 Number of warnings: 6 Number of CLBs: 133 out of 400 33% CLB Flip Flops: 104 CLB Latches: 0 4 input LUTs: 217 (2 used as route-throughs) 3 input LUTs: 23 (8 used as route-throughs) 32X1 ROMs: 12 Number of bonded IOBs: 45 out of 65 69% IOB Flops: 31 IOB Latches: 0 Number of TBUFs: 12 out of 880 1% Number of BUFGLSs: 2 out of 8 25% Number of RPM macros: 1 Total equivalent gate count for design: 4208 Additional JTAG gate count for IOBs: 2160 Writing design file "map.ncd"... Removed Logic Summary: 60 block(s) removed 15 block(s) optimized away 63 signal(s) removed Mapping completed. See MAP report file "map.mrp" for details. ================================================== par -w -ol 2 -d 0 map.ncd xbusvga.ncd xbusvga.pcf PAR: Xilinx Place And Route C.21. Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Constraints file: xbusvga.pcf Loading device database for application par from file "map.ncd". "xbusvga" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application par from file '4010xl.nph' in environment D:/Xilinx/fndtn. Device speed data version: C 1.1.2.2 FINAL. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 45 out of 61 73% Flops: 31 Latches: 0 Number of CLBs 133 out of 400 33% Total Latches: 0 out of 800 0% Total CLB Flops: 104 out of 800 13% 4 input LUTs: 241 out of 800 30% 3 input LUTs: 35 out of 400 8% Number of BUFGLSs 2 out of 8 25% Number of TBUFs 12 out of 880 1% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (set by user) Starting initial Placement phase. REAL time: 2 secs Finished initial Placement phase. REAL time: 3 secs Starting Constructive Placer. REAL time: 3 secs Placer score = 119030 Placer score = 107880 Placer score = 82900 Placer score = 75810 Placer score = 74520 Placer score = 72050 Placer score = 69380 Placer score = 67710 Placer score = 62420 Placer score = 59670 Placer score = 58280 Placer score = 57970 Placer score = 53770 Placer score = 49420 Placer score = 48290 Placer score = 46360 Placer score = 45550 Placer score = 45190 Placer score = 44560 Placer score = 44330 Placer score = 43540 Placer score = 42760 Placer score = 42590 Placer score = 42580 Placer score = 42460 Placer score = 42440 Finished Constructive Placer. REAL time: 9 secs Writing design to file "xbusvga.ncd". Starting Optimizing Placer. REAL time: 9 secs Optimizing Swapped 15 comps. Xilinx Placer [1] 42130 REAL time: 10 secs Finished Optimizing Placer. REAL time: 10 secs Writing design to file "xbusvga.ncd". Total REAL time to Placer completion: 10 secs Total CPU time to Placer completion: 10 secs 0 connection(s) routed; 1022 unrouted active, 23 unrouted PWR/GND. Starting router resource preassignment Completed router resource preassignment. REAL time: 11 secs Starting iterative routing. Routing active signals. End of iteration 1 1022 successful; 0 unrouted active, 23 unrouted PWR/GND; (0) REAL time: 12 secs End of iteration 2 1022 successful; 0 unrouted active, 23 unrouted PWR/GND; (0) REAL time: 13 secs Constraints are met. Routing PWR/GND nets. Power and ground nets completely routed. Writing design to file "xbusvga.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 1045 successful; 0 unrouted; (0) REAL time: 16 secs Writing design to file "xbusvga.ncd". Total REAL time: 16 secs Total CPU time: 15 secs End of route. 1045 routed (100.00%); 0 unrouted. No errors found. Completely routed. This design was run without timing constraints. It is likely that much better circuit performance can be obtained by trying either or both of the following: - Enabling the Delay Based Cleanup router pass, if not already enabled - Supplying timing constraints in the input design Total REAL time to Router completion: 16 secs Total CPU time to Router completion: 15 secs Generating PAR statistics. Writing design to file "xbusvga.ncd". All signals are completely routed. Total REAL time to PAR completion: 17 secs Total CPU time to PAR completion: 16 secs PAR done. ================================================== trce xbusvga.ncd xbusvga.pcf -e 3 -o xbusvga.twr Xilinx TRACE, Version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Loading device database for application trce from file "xbusvga.ncd". "xbusvga" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application trce from file '4010xl.nph' in environment D:/Xilinx/fndtn. -------------------------------------------------------------------------------- Xilinx TRACE, Version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Design file: xbusvga.ncd Physical constraint file: xbusvga.pcf Device,speed: xc4010xl,-3 (C 1.1.2.2 FINAL) Report level: error report -------------------------------------------------------------------------------- WARNING:Timing:181 - No timing constraints found, doing default enumeration. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 4294 paths, 312 nets, and 1022 connections (100.0% coverage) Design statistics: Minimum period: 34.787ns (Maximum frequency: 28.746MHz) Maximum combinational path delay: 37.709ns Maximum net delay: 16.141ns WARNING:Timing:33 - Clock nets using non-dedicated resources were found in this design. Clock skew on these resources will not be automatically addressed during path analysis. To create a timing report that analyzes clock skew for these paths, run trce with the '-skew' option. Analysis completed Thu May 18 17:14:06 2000 -------------------------------------------------------------------------------- Total time: 4 secs ================================================== ngdanno xbusvga.ncd map.ngm ngdanno: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Loading device database for application ngdanno from file "xbusvga.ncd". "xbusvga" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application ngdanno from file '4010xl.nph' in environment D:/Xilinx/fndtn. Reading .ngm file "map.ngm"... Building NGA image... Annotating NGA image... Distributing delays... WARNING:Anno:26 - NGDANNO found physical components for which 100 percent back-annotation is not possible. (These components are listed below.) Some reasons these components may not be fully back-annotatable include: 1. The logic was replicated during physical mapping. 2. MAP was directed to optimize the logic through use of the -oe or -os option, or the OPTIMIZE or OPT_EFFORT design attribute. 3. The component's configuration implies a more complex delay model than can be accurately represented in the original design logic. An example of such a configuration is an XC4000-family CLB containing both carry logic and multiple flip-flops. Simulation models for the following components will be constructed from the NCD netlist. Signal names buried within these components will be lost. H3/L4/MO0_0 H3/L4/MO0_1 H3/L4/MO0_2 H3/L4/MO0_3 H3/L4/MO0_4 H3/L4/MO0_5 H3/L4/MO1_0 H3/L4/MO1_1 H3/L4/MO1_2 H3/L4/MO1_3 H3/L4/MO1_4 H3/L4/MO1_5 HCNT<2> HCNT<4> HCNT<6> U5/C431_N26 U5/C432_N26 U5/C758_CINt U5/C760_CINt U5/N1398 U5/N1402 U5/N1404 U5/N1439 U5/N1443 U5/N1445 U5/N1447 U5/xstart<1> U5/xstart<3> U5/xstart<5> U5/ystart<1> U5/ystart<3> VCNT<2> VCNT<4> VCNT<6> XADDRESS<11> XADDRESS<13> XADDRESS<1> XADDRESS<3> XADDRESS<5> XADDRESS<7> XADDRESS<9> Writing .nga file "xbusvga.nga"... 150 logical models annotated 41 physical models annotated ================================================== ngd2edif -w -v fndtn xbusvga.nga time_sim.edn ngd2edif: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. writing only delay properties to EDIF file dedicated signals will be given global scope running NGD DRC ... writing EDIF file to 'time_sim.edn' ... ================================================== xcpy time_sim.edn C:\XBUS\XBUSVGA\time_sim.edn ================================================== bitgen xbusvga.ncd -l -w -f bitgen.ut BITGEN: Xilinx Bitstream Generator C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Loading device database for application Bitgen from file "xbusvga.ncd". "xbusvga" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application Bitgen from file '4010xl.nph' in environment D:/Xilinx/fndtn. Opened constraints file xbusvga.pcf. Thu May 18 17:14:28 2000 Running DRC. DRC detected 0 errors and 0 warnings. Saving ll file in "xbusvga.ll". Creating bit map... Saving bit stream in "xbusvga.bit". ================================================== xcpy xbusvga.bit C:\XBUS\XBUSVGA\xbusvga.bit ================================================== xcpy xbusvga.ll C:\XBUS\XBUSVGA\xbusvga.ll