module ReadDataReg (CLK,  ReadData, LDReadData, SHReadData, OutData) ;

input CLK ;
input [7:0] ReadData;		// Data being read
input LDReadData;			// Load register with data read
input SHReadData;			// Shift the ReadData out
output [3:0] OutData;		// Data to XBUS

reg [7:0] HoldData;			// Register to hold data being read

assign OutData = HoldData[3:0];  // Data is shifted right when sent

always @(posedge CLK) begin
	if (LDReadData) HoldData = ReadData;
	if (SHReadData) HoldData[3:0] = HoldData[7:4];	// Shift right
end

endmodule