// Xilinx XPort Language Converter, Version 4.1 (107)
// 
// ABEL    Design Source: 1
// Verilog Design Output: 1.v
// Created 16-May-2000 11:38 PM
//
// Copyright (c) 2000, Xilinx, Inc.  All Rights Reserved.
// Xilinx Inc makes no warranty, expressed or implied, with respect to
// the operation and/or functionality of the converted output files.
// 

//
//
// *** this module FAILED during conversion
//Look at error messages.
//