**** Interact v3.0.2.22 **** C Pcm #### Start Xilinx Foundation F2.1i - Messages - Thu May 18 16:49:55 2000 0 Pcm #### ---------- Opening project: c:\xbus\xbusvga ---------- 0 Pcm #### Design Type Schematic 0 Pcm #### Xilinx server initialization 0 Pcm #### Xilinx version: 1, 0, 0, 1 0 Pcm #### Opening Xilinx project 0 Pcm #### Reading Xilinx project 0 Pcm #### Execute fsm /p 898 0 Pcm #### Execute d:\xilinx\fndtn\active\exe\sc.exe 0 Pcm #### START: Schematic Editor C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA1.SCH 2 Sc #### Symbol [MEM2PORT] from library # 1014 found in library # 1017 2 Sc #### Symbol [VGACONTROL8] from library # 1014 found in library # 1017 2 Sc #### Symbol [BUSIFACE] from library # 1014 found in library # 1017 2 Sc #### Symbol [PAN] from library # 1014 found in library # 1017 C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires 0 Pcm #### Execute: zip32.exe R 0 ?? #### ZIP32: Project XBUSVGA has been successfully restored from \\Ifilesrv1\courses\cse477\Spring2000\Xbus\Xbusvga.zip to d:\477\xbus. 3 Pcm #### Application ZIP32 send message Open Project 0 Pcm #### ---------- Opening project: d:\477\xbus\xbusvga ---------- 3 Pcm #### Library d:\477\xbus\XBUSVGA\lib\XBUSVGA: old 1019 new 1021 0 Pcm #### Xilinx server initialization 0 Pcm #### Xilinx version: 1, 0, 0, 1 0 Pcm #### Opening Xilinx project 0 Pcm #### Design Type Schematic C Sc #### Loading sheet : D:\477\XBUS\XBUSVGA\VGA1.SCH 2 Sc #### Symbol [BUSIFACE] from library # 1019 found in library # 1021 C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : D:\477\XBUS\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires 0 Pcm #### Reading Xilinx project C Sc #### Loading sheet : D:\477\XBUS\XBUSVGA\VGA1.SCH 2 Sc #### Symbol [BUSIFACE] from library # 1019 found in library # 1021 C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : SHEET - /D:\477\XBUS\XBUSVGA\VGA1.SCH/H5 - BUSIFACE 2 Sc #### Symbol [BUSCONTROL] from library # 1014 found in library # 1021 2 Sc #### Symbol [ADDRDATAREGS] from library # 1014 found in library # 1021 2 Sc #### Symbol [OUTRIBUF4] from library # 1014 found in library # 1021 2 Sc #### Symbol [TRIPAD4] from library # 1014 found in library # 1021 2 Sc #### Symbol [READDATAREG] from library # 1014 found in library # 1021 C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires 0 Pcm #### EXIT: Schematic Editor 0 Pcm #### START: Schematic Editor C Sc #### Loading sheet : D:\477\XBUS\XBUSVGA\VGA1.SCH 2 Sc #### Symbol [BUSIFACE] from library # 1019 found in library # 1021 C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : D:\477\XBUS\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires 0 Pcm #### EXIT: Schematic Editor 0 Pcm #### Execute: zip32.exe R 0 ?? #### ZIP32: Project XBUSVGA has been successfully restored from \\Ifilesrv1\courses\cse477\Spring2000\Xbus\OLD\Xbusvga.zip to c:\temp. 3 Pcm #### Application ZIP32 send message Open Project 0 Pcm #### ---------- Opening project: c:\temp\xbusvga ---------- 3 Pcm #### Library c:\temp\XBUSVGA\lib\XBUSVGA: old 1014 new 1022 0 Pcm #### Xilinx server initialization 0 Pcm #### Xilinx version: 1, 0, 0, 1 0 Pcm #### Opening Xilinx project 0 Pcm #### Design Type Schematic 0 Pcm #### Reading Xilinx project 0 Pcm #### START: Schematic Editor C Sc #### Loading sheet : C:\TEMP\XBUSVGA\VGA1.SCH 2 Sc #### Symbol [MEM2PORT] from library # 1014 found in library # 1022 2 Sc #### Symbol [VGACONTROL8] from library # 1014 found in library # 1022 2 Sc #### Symbol [BUSIFACE] from library # 1014 found in library # 1022 2 Sc #### Symbol [PAN] from library # 1014 found in library # 1022 C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\TEMP\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\TEMP\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\TEMP\XBUSVGA\VGA1.SCH 2 Sc #### Symbol [MEM2PORT] from library # 1014 found in library # 1022 2 Sc #### Symbol [VGACONTROL8] from library # 1014 found in library # 1022 2 Sc #### Symbol [BUSIFACE] from library # 1014 found in library # 1022 2 Sc #### Symbol [PAN] from library # 1014 found in library # 1022 C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires 3 Pcm #### Application SC send message Update Sheet 0 Pcm #### EXIT: Schematic Editor C Conv #### Scanning design for HDL macros and LogiBLOX symbols C Conv #### C:\TEMP\XBUSVGA\XBUSVGA.alb C Conv #### BUSIFACE C Conv #### MEM2PORT C Conv #### VGACONTROL8 W Pcm #### Schematic netlist xbusvga is older than schematic W Pcm #### Update netlist from Schematic Editor 0 Pcm #### START: Schematic Editor C Sc #### Loading sheet : C:\TEMP\XBUSVGA\VGA1.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\TEMP\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Netlist generation in progress C Sc #### Creating netlist from schematic [C:\TEMP\XBUSVGA\VGA1.SCH] W Sc #### Warnning: multiple drivers or sourceless/loadless nets detected W Sc #### Sourceless net: CLK W Sc #### Sourceless net: PC_D0 W Sc #### Loadless net: XADDRESS15 W Sc #### -------------------------- W Sc #### Warning: unconnected input and output pins detected W Sc #### Unconnected output pin: READREG (H5) W Sc #### Unconnected output pin: STATE[3:0] (H5) W Sc #### Unconnected output pin: Q[7:0] ($I133) C Sc #### Creating netlist from schematic [C:\TEMP\XBUSVGA\VGA2.SCH] W Sc #### Warnning: multiple drivers or sourceless/loadless nets detected W Sc #### Loadless net: PC_D3 W Sc #### Loadless net: PC_D5 W Sc #### Loadless net: PC_D1 W Sc #### Loadless net: PC_D2 W Sc #### Loadless net: PC_D7 W Sc #### Loadless net: PC_D6 W Sc #### Sourceless net: PC_S7 W Sc #### Sourceless net: PC_S5 W Sc #### Loadless net: PC_D4 W Sc #### Loadless net: CLK W Sc #### Sourceless net: LED0 W Sc #### Sourceless net: LED1 W Sc #### Sourceless net: LED2 W Sc #### Sourceless net: LED3 W Sc #### Sourceless net: LED4 W Sc #### Sourceless net: LED5 W Sc #### Sourceless net: LED6 C Sc #### Netlist created successfully 0 Pcm #### EXIT: Schematic Editor 0 Pcm #### Netlist created successfully W Pcm #### Edif netlist xbusvga is older than schematic netlist W Pcm #### Update Edif Netlist C Conv #### Export netlist 'C:\TEMP\XBUSVGA\xbusvga.ALB' to EDIF 200 C Conv #### Macro 'MEMCONTROL' not exported. File 'C:\TEMP\XBUSVGA\MEMCONTROL.xnf' exists C Conv #### Macro 'PAN' not exported. File 'C:\TEMP\XBUSVGA\PAN.xnf' exists C Conv #### Macro 'READDATAREG' not exported. File 'C:\TEMP\XBUSVGA\READDATAREG.xnf' exists C Conv #### Macro 'SYNCGEN' not exported. File 'C:\TEMP\XBUSVGA\SYNCGEN.xnf' exists C Conv #### Macro 'ADDRDATAREGS' not exported. File 'C:\TEMP\XBUSVGA\ADDRDATAREGS.xnf' exists C Conv #### Macro 'BLANKPIXEL' not exported. File 'C:\TEMP\XBUSVGA\BLANKPIXEL.xnf' exists C Conv #### Macro 'BUSCONTROL' not exported. File 'C:\TEMP\XBUSVGA\BUSCONTROL.xnf' exists C Conv #### Total number of instances: 132 C Conv #### Total number of nets: 408 C Conv #### EDIF netlist exported to file - C:\TEMP\XBUSVGA\xbusvga.edn 0 Pcm #### Netlist created successfully 0 Pcm #### ver1->rev1 Simulation Template "Foundation EDIF" set. 0 Pcm #### Flow Engine is running (ver1->rev1). 3 Pcm #### Application SC send message Update Sheet 3 Pcm #### Application SC send message Update Sheet 3 Pcm #### Application CONV_ACS send message Add Report C Xie #### Flow Engine: ver1->rev1 (New OK) C Xie #### Flow Engine: ver1->rev1 (Translated OK) 0 Pcm #### Execute: d:\xilinx\fndtn\active\exe\rbrowser.exe C Xie #### Flow Engine: ver1->rev1 (Mapped OK) C Xie #### Flow Engine: ver1->rev1 (Routed OK) C Xie #### Flow Engine: ver1->rev1 (Timed OK) C Xie #### Flow Engine: ver1->rev1 (Implemented OK) C Xie #### Flow Engine ver1->rev1 Completed Successfully. 0 Pcm #### Execute: zip32.exe A "C:\TEMP\XBUSVGA.pdf" 0 ?? #### ZIP32: Project XBUSVGA has been successfully archived from C:\TEMP to C:\TEMP\XBUSVGA.ZIP. 0 Pcm #### Execute: zip32.exe A "C:\TEMP\XBUSVGA.pdf" W ?? #### ZIP32: User break. 0 Pcm #### Execute: zip32.exe R 0 ?? #### ZIP32: Project XBUSVGA has been successfully restored from \\Ifilesrv1\courses\cse477\Spring2000\Xbus\OLD\Xbusvga.zip to c:\xbus. 3 Pcm #### Application ZIP32 send message Open Project 0 Pcm #### ---------- Opening project: c:\xbus\xbusvga ---------- 3 Pcm #### Library c:\xbus\XBUSVGA\lib\XBUSVGA: old 1014 new 1017 0 Pcm #### Xilinx server initialization 0 Pcm #### Xilinx version: 1, 0, 0, 1 0 Pcm #### Opening Xilinx project 0 Pcm #### Design Type Schematic 0 Pcm #### Reading Xilinx project 0 Pcm #### Execute d:\xilinx\fndtn\active\exe\sc.exe 0 Pcm #### START: Schematic Editor C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA1.SCH 2 Sc #### Symbol [MEM2PORT] from library # 1014 found in library # 1017 2 Sc #### Symbol [VGACONTROL8] from library # 1014 found in library # 1017 2 Sc #### Symbol [BUSIFACE] from library # 1014 found in library # 1017 2 Sc #### Symbol [PAN] from library # 1014 found in library # 1017 C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA1.SCH 2 Sc #### Symbol [MEM2PORT] from library # 1014 found in library # 1017 2 Sc #### Symbol [VGACONTROL8] from library # 1014 found in library # 1017 2 Sc #### Symbol [BUSIFACE] from library # 1014 found in library # 1017 2 Sc #### Symbol [PAN] from library # 1014 found in library # 1017 C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires 3 Pcm #### Application SC send message Update Sheet C Sc #### Loading sheet : SHEET - /C:\XBUS\XBUSVGA\VGA1.SCH/H5 - BUSIFACE 2 Sc #### Symbol [BUSCONTROL] from library # 1014 found in library # 1017 2 Sc #### Symbol [ADDRDATAREGS] from library # 1014 found in library # 1017 2 Sc #### Symbol [OUTRIBUF4] from library # 1014 found in library # 1017 2 Sc #### Symbol [TRIPAD4] from library # 1014 found in library # 1017 2 Sc #### Symbol [READDATAREG] from library # 1014 found in library # 1017 C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : SHEET - /C:\XBUS\XBUSVGA\VGA1.SCH/H5 - BUSIFACE 2 Sc #### Symbol [BUSCONTROL] from library # 1014 found in library # 1017 2 Sc #### Symbol [ADDRDATAREGS] from library # 1014 found in library # 1017 2 Sc #### Symbol [OUTRIBUF4] from library # 1014 found in library # 1017 2 Sc #### Symbol [TRIPAD4] from library # 1014 found in library # 1017 2 Sc #### Symbol [READDATAREG] from library # 1014 found in library # 1017 C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires 0 Pcm #### EXIT: Schematic Editor 0 Pcm #### Execute d:\xilinx\fndtn\active\exe\sc.exe 0 Pcm #### START: Schematic Editor C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA1.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires 0 Pcm #### EXIT: Schematic Editor C Conv #### Scanning design for HDL macros and LogiBLOX symbols C Conv #### C:\XBUS\XBUSVGA\XBUSVGA.alb C Conv #### BUSIFACE C Conv #### MEM2PORT C Conv #### VGACONTROL8 W Pcm #### Schematic netlist xbusvga is older than schematic W Pcm #### Update netlist from Schematic Editor 0 Pcm #### START: Schematic Editor C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA1.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Netlist generation in progress C Sc #### Creating netlist from schematic [C:\XBUS\XBUSVGA\VGA1.SCH] W Sc #### Warnning: multiple drivers or sourceless/loadless nets detected W Sc #### Sourceless net: CLK W Sc #### Sourceless net: PC_D0 W Sc #### Loadless net: XADDRESS15 W Sc #### -------------------------- W Sc #### Warning: unconnected input and output pins detected W Sc #### Unconnected output pin: READREG (H5) W Sc #### Unconnected output pin: STATE[3:0] (H5) W Sc #### Unconnected output pin: Q[7:0] ($I133) C Sc #### Creating netlist from schematic [C:\XBUS\XBUSVGA\VGA2.SCH] W Sc #### Warnning: multiple drivers or sourceless/loadless nets detected W Sc #### Loadless net: PC_D3 W Sc #### Loadless net: PC_D5 W Sc #### Loadless net: PC_D1 W Sc #### Loadless net: PC_D2 W Sc #### Loadless net: PC_D7 W Sc #### Loadless net: PC_D6 W Sc #### Sourceless net: PC_S7 W Sc #### Sourceless net: PC_S5 W Sc #### Loadless net: PC_D4 W Sc #### Loadless net: CLK W Sc #### Sourceless net: LED0 W Sc #### Sourceless net: LED1 W Sc #### Sourceless net: LED2 W Sc #### Sourceless net: LED3 W Sc #### Sourceless net: LED4 W Sc #### Sourceless net: LED5 W Sc #### Sourceless net: LED6 C Sc #### Netlist created successfully 0 Pcm #### EXIT: Schematic Editor 0 Pcm #### Netlist created successfully W Pcm #### Edif netlist xbusvga is older than schematic netlist W Pcm #### Update Edif Netlist C Conv #### Export netlist 'C:\XBUS\XBUSVGA\xbusvga.ALB' to EDIF 200 C Conv #### Macro 'MEMCONTROL' not exported. File 'C:\XBUS\XBUSVGA\MEMCONTROL.xnf' exists C Conv #### Macro 'PAN' not exported. File 'C:\XBUS\XBUSVGA\PAN.xnf' exists C Conv #### Macro 'READDATAREG' not exported. File 'C:\XBUS\XBUSVGA\READDATAREG.xnf' exists C Conv #### Macro 'SYNCGEN' not exported. File 'C:\XBUS\XBUSVGA\SYNCGEN.xnf' exists C Conv #### Macro 'ADDRDATAREGS' not exported. File 'C:\XBUS\XBUSVGA\ADDRDATAREGS.xnf' exists C Conv #### Macro 'BLANKPIXEL' not exported. File 'C:\XBUS\XBUSVGA\BLANKPIXEL.xnf' exists C Conv #### Macro 'BUSCONTROL' not exported. File 'C:\XBUS\XBUSVGA\BUSCONTROL.xnf' exists C Conv #### Total number of instances: 132 C Conv #### Total number of nets: 408 C Conv #### EDIF netlist exported to file - C:\XBUS\XBUSVGA\xbusvga.edn 0 Pcm #### Netlist created successfully 0 Pcm #### ver1->rev1 Simulation Template "Foundation EDIF" set. 0 Pcm #### Flow Engine is running (ver1->rev1). 3 Pcm #### Application SC send message Update Sheet 3 Pcm #### Application SC send message Update Sheet 3 Pcm #### Application CONV_ACS send message Add Report C Xie #### Flow Engine: ver1->rev1 (New OK) C Xie #### Flow Engine: ver1->rev1 (Translated OK) C Xie #### Flow Engine: ver1->rev1 (Mapped OK) C Xie #### Flow Engine: ver1->rev1 (Routed OK) C Xie #### Flow Engine: ver1->rev1 (Timed OK) C Xie #### Flow Engine: ver1->rev1 (Implemented OK) C Xie #### Flow Engine ver1->rev1 Completed Successfully. 0 Pcm #### Execute d:\xilinx\fndtn\active\exe\sc.exe 0 Pcm #### START: Schematic Editor C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA1.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires 0 Pcm #### ---------- Opening project: c:\xbus\xbusvga ---------- 0 Pcm #### Xilinx server initialization 0 Pcm #### Xilinx version: 1, 0, 0, 1 0 Pcm #### Opening Xilinx project 0 Pcm #### Design Type Schematic C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA1.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires C Sc #### Loading sheet : C:\XBUS\XBUSVGA\VGA2.SCH C Sc #### Sheet loaded 3 Sc #### Checking connections with symbols 3 Sc #### Checking terminal positions 3 Sc #### Checking wires 0 Pcm #### Reading Xilinx project 0 Pcm #### EXIT: Schematic Editor 0 Pcm #### Execute: zip32.exe A "C:\XBUS\XBUSVGA.pdf"